ExtraV: Boosting graph processing near storage with a coherent accelerator

Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi Joon Nam, Mark R. Nutter, Damir Jamsek

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

In this paper, we propose ExtraV, a framework for near-storage graph processing. It is based on the novel concept of graph virtualization, which efficiently utilizes a cache-coherent hardware accelerator at the storage side to achieve performance and exibility at the same time. ExtraV consists of four main components: 1) host processor, 2) main memory, 3) AFU (Accelerator Function Unit) and 4) storage. The AFU, a hardware accelerator, sits between the host processor and storage. Using a coherent interface that allows main memory accesses, it performs graph traversal functions that are common to various algorithms while the program running on the host processor (called the host program) manages the overall execution along with more application-specific tasks. Graph virtualization is a high-level programming model of graph processing that allows designers to focus on algorithm-specific functions. Realized by the accelerator, graph virtualization gives the host programs an illusion that the graph data reside on the main memory in a layout that fits with the memory access behavior of host programs even though the graph data are actually stored in a multi-level, compressed form in storage. We prototyped ExtraV on a Power8 machine with a CAPI-enabled FPGA. Our experiments on a real system prototype offer significant speedup compared to state-of-the-art software only implementations.

Original languageEnglish
Pages (from-to)1706-1717
Number of pages12
JournalProceedings of the VLDB Endowment
Volume10
Issue number12
Publication statusPublished - 2017 Aug 1
Event43rd International Conference on Very Large Data Bases, VLDB 2017 - Munich, Germany
Duration: 2017 Aug 282017 Sep 1

Fingerprint

Particle accelerators
Data storage equipment
Processing
Computer hardware
Computer programming
Interfaces (computer)
Program processors
Field programmable gate arrays (FPGA)
Virtualization
Experiments

All Science Journal Classification (ASJC) codes

  • Computer Science (miscellaneous)
  • Computer Science(all)

Cite this

Lee, J., Kim, H., Yoo, S., Choi, K., Hofstee, H. P., Nam, G. J., ... Jamsek, D. (2017). ExtraV: Boosting graph processing near storage with a coherent accelerator. Proceedings of the VLDB Endowment, 10(12), 1706-1717.
Lee, Jinho ; Kim, Heesu ; Yoo, Sungjoo ; Choi, Kiyoung ; Hofstee, H. Peter ; Nam, Gi Joon ; Nutter, Mark R. ; Jamsek, Damir. / ExtraV : Boosting graph processing near storage with a coherent accelerator. In: Proceedings of the VLDB Endowment. 2017 ; Vol. 10, No. 12. pp. 1706-1717.
@article{8e9a99ad0f3e48898d762a766941e3b2,
title = "ExtraV: Boosting graph processing near storage with a coherent accelerator",
abstract = "In this paper, we propose ExtraV, a framework for near-storage graph processing. It is based on the novel concept of graph virtualization, which efficiently utilizes a cache-coherent hardware accelerator at the storage side to achieve performance and exibility at the same time. ExtraV consists of four main components: 1) host processor, 2) main memory, 3) AFU (Accelerator Function Unit) and 4) storage. The AFU, a hardware accelerator, sits between the host processor and storage. Using a coherent interface that allows main memory accesses, it performs graph traversal functions that are common to various algorithms while the program running on the host processor (called the host program) manages the overall execution along with more application-specific tasks. Graph virtualization is a high-level programming model of graph processing that allows designers to focus on algorithm-specific functions. Realized by the accelerator, graph virtualization gives the host programs an illusion that the graph data reside on the main memory in a layout that fits with the memory access behavior of host programs even though the graph data are actually stored in a multi-level, compressed form in storage. We prototyped ExtraV on a Power8 machine with a CAPI-enabled FPGA. Our experiments on a real system prototype offer significant speedup compared to state-of-the-art software only implementations.",
author = "Jinho Lee and Heesu Kim and Sungjoo Yoo and Kiyoung Choi and Hofstee, {H. Peter} and Nam, {Gi Joon} and Nutter, {Mark R.} and Damir Jamsek",
year = "2017",
month = "8",
day = "1",
language = "English",
volume = "10",
pages = "1706--1717",
journal = "Proceedings of the VLDB Endowment",
issn = "2150-8097",
publisher = "Very Large Data Base Endowment Inc.",
number = "12",

}

Lee, J, Kim, H, Yoo, S, Choi, K, Hofstee, HP, Nam, GJ, Nutter, MR & Jamsek, D 2017, 'ExtraV: Boosting graph processing near storage with a coherent accelerator', Proceedings of the VLDB Endowment, vol. 10, no. 12, pp. 1706-1717.

ExtraV : Boosting graph processing near storage with a coherent accelerator. / Lee, Jinho; Kim, Heesu; Yoo, Sungjoo; Choi, Kiyoung; Hofstee, H. Peter; Nam, Gi Joon; Nutter, Mark R.; Jamsek, Damir.

In: Proceedings of the VLDB Endowment, Vol. 10, No. 12, 01.08.2017, p. 1706-1717.

Research output: Contribution to journalConference article

TY - JOUR

T1 - ExtraV

T2 - Boosting graph processing near storage with a coherent accelerator

AU - Lee, Jinho

AU - Kim, Heesu

AU - Yoo, Sungjoo

AU - Choi, Kiyoung

AU - Hofstee, H. Peter

AU - Nam, Gi Joon

AU - Nutter, Mark R.

AU - Jamsek, Damir

PY - 2017/8/1

Y1 - 2017/8/1

N2 - In this paper, we propose ExtraV, a framework for near-storage graph processing. It is based on the novel concept of graph virtualization, which efficiently utilizes a cache-coherent hardware accelerator at the storage side to achieve performance and exibility at the same time. ExtraV consists of four main components: 1) host processor, 2) main memory, 3) AFU (Accelerator Function Unit) and 4) storage. The AFU, a hardware accelerator, sits between the host processor and storage. Using a coherent interface that allows main memory accesses, it performs graph traversal functions that are common to various algorithms while the program running on the host processor (called the host program) manages the overall execution along with more application-specific tasks. Graph virtualization is a high-level programming model of graph processing that allows designers to focus on algorithm-specific functions. Realized by the accelerator, graph virtualization gives the host programs an illusion that the graph data reside on the main memory in a layout that fits with the memory access behavior of host programs even though the graph data are actually stored in a multi-level, compressed form in storage. We prototyped ExtraV on a Power8 machine with a CAPI-enabled FPGA. Our experiments on a real system prototype offer significant speedup compared to state-of-the-art software only implementations.

AB - In this paper, we propose ExtraV, a framework for near-storage graph processing. It is based on the novel concept of graph virtualization, which efficiently utilizes a cache-coherent hardware accelerator at the storage side to achieve performance and exibility at the same time. ExtraV consists of four main components: 1) host processor, 2) main memory, 3) AFU (Accelerator Function Unit) and 4) storage. The AFU, a hardware accelerator, sits between the host processor and storage. Using a coherent interface that allows main memory accesses, it performs graph traversal functions that are common to various algorithms while the program running on the host processor (called the host program) manages the overall execution along with more application-specific tasks. Graph virtualization is a high-level programming model of graph processing that allows designers to focus on algorithm-specific functions. Realized by the accelerator, graph virtualization gives the host programs an illusion that the graph data reside on the main memory in a layout that fits with the memory access behavior of host programs even though the graph data are actually stored in a multi-level, compressed form in storage. We prototyped ExtraV on a Power8 machine with a CAPI-enabled FPGA. Our experiments on a real system prototype offer significant speedup compared to state-of-the-art software only implementations.

UR - http://www.scopus.com/inward/record.url?scp=85036650825&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85036650825&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:85036650825

VL - 10

SP - 1706

EP - 1717

JO - Proceedings of the VLDB Endowment

JF - Proceedings of the VLDB Endowment

SN - 2150-8097

IS - 12

ER -

Lee J, Kim H, Yoo S, Choi K, Hofstee HP, Nam GJ et al. ExtraV: Boosting graph processing near storage with a coherent accelerator. Proceedings of the VLDB Endowment. 2017 Aug 1;10(12):1706-1717.