Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure

B. T. Lee, J. W. Park, K. S. Park, C. H. Lee, S. W. Paik, S. D. Lee, Jung B. Choi, K. S. Min, J. S. Park, S. Y. Hahn, T. J. Park, H. Shin, S. C. Hong, Kwyro Lee, H. C. Kwon, S. I. Park, K. T. Kim, K. H. Yoo

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)

Abstract

A new device structure for a single-electron-tunnelling transistor with a dual-gate geometry has been fabricated based on the silicon-on-insulator structure prepared by SIMOX wafers. The split gate of the transistor is the lower-level gate and located ∼20 nm above the inversion layer 2DEG active channel, which yields strong carrier confinement with a fully controllable tunnelling potential barrier. The transistor operates at low temperatures and exhibits single-electron tunnelling behavior through a nano-size quantum dot. The Coulomb blockade oscillation is demonstrated at 15 mK and its periodicity is 16.4 mV in the upper gate voltage. For the nonlinear transport regime, Coulomb staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics near zero bias display a typical Coulomb gap due to the one-electron charging effect. From the width of the blockade regime the dot capacitance is estimated to be ∼13 aF.

Original languageEnglish
Pages (from-to)1463-1467
Number of pages5
JournalSemiconductor Science and Technology
Volume13
Issue number12
DOIs
Publication statusPublished - 1998 Dec

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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