Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure

B. T. Lee, J. W. Park, K. S. Park, C. H. Lee, S. W. Paik, S. D. Lee, Jung B. Choi, K. S. Min, J. S. Park, S. Y. Hahn, T. J. Park, H. Shin, S. C. Hong, Kwyro Lee, H. C. Kwon, S. I. Park, K. T. Kim, Kyung-hwa Yoo

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A new device structure for a single-electron-tunnelling transistor with a dual-gate geometry has been fabricated based on the silicon-on-insulator structure prepared by SIMOX wafers. The split gate of the transistor is the lower-level gate and located ∼20 nm above the inversion layer 2DEG active channel, which yields strong carrier confinement with a fully controllable tunnelling potential barrier. The transistor operates at low temperatures and exhibits single-electron tunnelling behavior through a nano-size quantum dot. The Coulomb blockade oscillation is demonstrated at 15 mK and its periodicity is 16.4 mV in the upper gate voltage. For the nonlinear transport regime, Coulomb staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics near zero bias display a typical Coulomb gap due to the one-electron charging effect. From the width of the blockade regime the dot capacitance is estimated to be ∼13 aF.

Original languageEnglish
Pages (from-to)1463-1467
Number of pages5
JournalSemiconductor Science and Technology
Volume13
Issue number12
DOIs
Publication statusPublished - 1998 Dec 1

Fingerprint

Coulomb blockade
Silicon
Transistors
transistors
Electron tunneling
insulators
Fabrication
fabrication
silicon
electron tunneling
Inversion layers
Two dimensional electron gas
Semiconductor quantum dots
stairways
Capacitance
charging
periodic variations
Geometry
Electrons
capacitance

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Lee, B. T. ; Park, J. W. ; Park, K. S. ; Lee, C. H. ; Paik, S. W. ; Lee, S. D. ; Choi, Jung B. ; Min, K. S. ; Park, J. S. ; Hahn, S. Y. ; Park, T. J. ; Shin, H. ; Hong, S. C. ; Lee, Kwyro ; Kwon, H. C. ; Park, S. I. ; Kim, K. T. ; Yoo, Kyung-hwa. / Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure. In: Semiconductor Science and Technology. 1998 ; Vol. 13, No. 12. pp. 1463-1467.
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abstract = "A new device structure for a single-electron-tunnelling transistor with a dual-gate geometry has been fabricated based on the silicon-on-insulator structure prepared by SIMOX wafers. The split gate of the transistor is the lower-level gate and located ∼20 nm above the inversion layer 2DEG active channel, which yields strong carrier confinement with a fully controllable tunnelling potential barrier. The transistor operates at low temperatures and exhibits single-electron tunnelling behavior through a nano-size quantum dot. The Coulomb blockade oscillation is demonstrated at 15 mK and its periodicity is 16.4 mV in the upper gate voltage. For the nonlinear transport regime, Coulomb staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics near zero bias display a typical Coulomb gap due to the one-electron charging effect. From the width of the blockade regime the dot capacitance is estimated to be ∼13 aF.",
author = "Lee, {B. T.} and Park, {J. W.} and Park, {K. S.} and Lee, {C. H.} and Paik, {S. W.} and Lee, {S. D.} and Choi, {Jung B.} and Min, {K. S.} and Park, {J. S.} and Hahn, {S. Y.} and Park, {T. J.} and H. Shin and Hong, {S. C.} and Kwyro Lee and Kwon, {H. C.} and Park, {S. I.} and Kim, {K. T.} and Kyung-hwa Yoo",
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Lee, BT, Park, JW, Park, KS, Lee, CH, Paik, SW, Lee, SD, Choi, JB, Min, KS, Park, JS, Hahn, SY, Park, TJ, Shin, H, Hong, SC, Lee, K, Kwon, HC, Park, SI, Kim, KT & Yoo, K 1998, 'Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure', Semiconductor Science and Technology, vol. 13, no. 12, pp. 1463-1467. https://doi.org/10.1088/0268-1242/13/12/024

Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure. / Lee, B. T.; Park, J. W.; Park, K. S.; Lee, C. H.; Paik, S. W.; Lee, S. D.; Choi, Jung B.; Min, K. S.; Park, J. S.; Hahn, S. Y.; Park, T. J.; Shin, H.; Hong, S. C.; Lee, Kwyro; Kwon, H. C.; Park, S. I.; Kim, K. T.; Yoo, Kyung-hwa.

In: Semiconductor Science and Technology, Vol. 13, No. 12, 01.12.1998, p. 1463-1467.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure

AU - Lee, B. T.

AU - Park, J. W.

AU - Park, K. S.

AU - Lee, C. H.

AU - Paik, S. W.

AU - Lee, S. D.

AU - Choi, Jung B.

AU - Min, K. S.

AU - Park, J. S.

AU - Hahn, S. Y.

AU - Park, T. J.

AU - Shin, H.

AU - Hong, S. C.

AU - Lee, Kwyro

AU - Kwon, H. C.

AU - Park, S. I.

AU - Kim, K. T.

AU - Yoo, Kyung-hwa

PY - 1998/12/1

Y1 - 1998/12/1

N2 - A new device structure for a single-electron-tunnelling transistor with a dual-gate geometry has been fabricated based on the silicon-on-insulator structure prepared by SIMOX wafers. The split gate of the transistor is the lower-level gate and located ∼20 nm above the inversion layer 2DEG active channel, which yields strong carrier confinement with a fully controllable tunnelling potential barrier. The transistor operates at low temperatures and exhibits single-electron tunnelling behavior through a nano-size quantum dot. The Coulomb blockade oscillation is demonstrated at 15 mK and its periodicity is 16.4 mV in the upper gate voltage. For the nonlinear transport regime, Coulomb staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics near zero bias display a typical Coulomb gap due to the one-electron charging effect. From the width of the blockade regime the dot capacitance is estimated to be ∼13 aF.

AB - A new device structure for a single-electron-tunnelling transistor with a dual-gate geometry has been fabricated based on the silicon-on-insulator structure prepared by SIMOX wafers. The split gate of the transistor is the lower-level gate and located ∼20 nm above the inversion layer 2DEG active channel, which yields strong carrier confinement with a fully controllable tunnelling potential barrier. The transistor operates at low temperatures and exhibits single-electron tunnelling behavior through a nano-size quantum dot. The Coulomb blockade oscillation is demonstrated at 15 mK and its periodicity is 16.4 mV in the upper gate voltage. For the nonlinear transport regime, Coulomb staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics near zero bias display a typical Coulomb gap due to the one-electron charging effect. From the width of the blockade regime the dot capacitance is estimated to be ∼13 aF.

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U2 - 10.1088/0268-1242/13/12/024

DO - 10.1088/0268-1242/13/12/024

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VL - 13

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EP - 1467

JO - Semiconductor Science and Technology

JF - Semiconductor Science and Technology

SN - 0268-1242

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