Fail Memory Configuration Set for RA Estimation

Hayoung Lee, Keewon Cho, Sungho Kang, Wooheon Kang, Seungtaek Lee, Woosik Jeong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

Original languageEnglish
Title of host publication2020 IEEE International Test Conference, ITC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728191133
DOIs
Publication statusPublished - 2020 Nov 1
Event2020 IEEE International Test Conference, ITC 2020 - Washington, United States
Duration: 2020 Nov 12020 Nov 6

Publication series

NameProceedings - International Test Conference
Volume2020-November
ISSN (Print)1089-3539

Conference

Conference2020 IEEE International Test Conference, ITC 2020
Country/TerritoryUnited States
CityWashington
Period20/11/120/11/6

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This paper was result of the research project supported by SK hynix Inc.

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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