Fail Memory Configuration Set for RA Estimation

Hayoung Lee; Keewon Cho; Sungho Kang; Wooheon Kang; Seungtaek Lee; Woosik Jeong

doi:10.1109/ITC44778.2020.9325273

Fail Memory Configuration Set for RA Estimation

Hayoung Lee, Keewon Cho, Sungho Kang, Wooheon Kang, Seungtaek Lee, Woosik Jeong

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

Original language	English
Title of host publication	2020 IEEE International Test Conference, ITC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728191133
DOIs	https://doi.org/10.1109/ITC44778.2020.9325273
Publication status	Published - 2020 Nov 1
Event	2020 IEEE International Test Conference, ITC 2020 - Washington, United States Duration: 2020 Nov 1 → 2020 Nov 6

Publication series

Name	Proceedings - International Test Conference
Volume	2020-November
ISSN (Print)	1089-3539

Conference

Conference	2020 IEEE International Test Conference, ITC 2020
Country/Territory	United States
City	Washington
Period	20/11/1 → 20/11/6

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This paper was result of the research project supported by SK hynix Inc.

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/ITC44778.2020.9325273

Cite this

@inproceedings{471abdf061a4404ca71ed4a369b1fa72,

title = "Fail Memory Configuration Set for RA Estimation",

abstract = "Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set. ",

author = "Hayoung Lee and Keewon Cho and Sungho Kang and Wooheon Kang and Seungtaek Lee and Woosik Jeong",

note = "Funding Information: ACKNOWLEDGMENT This paper was result of the research project supported by SK hynix Inc. Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE International Test Conference, ITC 2020 ; Conference date: 01-11-2020 Through 06-11-2020",

year = "2020",

month = nov,

day = "1",

doi = "10.1109/ITC44778.2020.9325273",

language = "English",

series = "Proceedings - International Test Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE International Test Conference, ITC 2020",

address = "United States",

}

Lee, H, Cho, K, Kang, S, Kang, W, Lee, S & Jeong, W 2020, Fail Memory Configuration Set for RA Estimation. in 2020 IEEE International Test Conference, ITC 2020., 9325273, Proceedings - International Test Conference, vol. 2020-November, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE International Test Conference, ITC 2020, Washington, United States, 20/11/1. https://doi.org/10.1109/ITC44778.2020.9325273

Fail Memory Configuration Set for RA Estimation. / Lee, Hayoung; Cho, Keewon; Kang, Sungho; Kang, Wooheon; Lee, Seungtaek; Jeong, Woosik.

2020 IEEE International Test Conference, ITC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9325273 (Proceedings - International Test Conference; Vol. 2020-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Fail Memory Configuration Set for RA Estimation

AU - Lee, Hayoung

AU - Cho, Keewon

AU - Kang, Sungho

AU - Kang, Wooheon

AU - Lee, Seungtaek

AU - Jeong, Woosik

PY - 2020/11/1

Y1 - 2020/11/1

N2 - Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

AB - Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

UR - http://www.scopus.com/inward/record.url?scp=85100180811&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85100180811&partnerID=8YFLogxK

U2 - 10.1109/ITC44778.2020.9325273

DO - 10.1109/ITC44778.2020.9325273

M3 - Conference contribution

AN - SCOPUS:85100180811

T3 - Proceedings - International Test Conference

BT - 2020 IEEE International Test Conference, ITC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE International Test Conference, ITC 2020

Y2 - 1 November 2020 through 6 November 2020

ER -

Fail Memory Configuration Set for RA Estimation

Abstract

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Bibliographical note

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