Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.
|Title of host publication||2020 IEEE International Test Conference, ITC 2020|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2020 Nov 1|
|Event||2020 IEEE International Test Conference, ITC 2020 - Washington, United States|
Duration: 2020 Nov 1 → 2020 Nov 6
|Name||Proceedings - International Test Conference|
|Conference||2020 IEEE International Test Conference, ITC 2020|
|Period||20/11/1 → 20/11/6|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This paper was result of the research project supported by SK hynix Inc.
© 2020 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics