Failure bitmap compression method for 3D-IC redundancy analysis

Keewon Cho, Woosung Lee, Jooyoung Kim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages335-336
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Feb 8
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2015 Nov 22015 Nov 5

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Other

Other12th International SoC Design Conference, ISOCC 2015
CountryKorea, Republic of
CityGyeongju
Period15/11/215/11/5

Fingerprint

Redundancy
Repair
Hardware
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Cho, K., Lee, W., Kim, J., & Kang, S. (2016). Failure bitmap compression method for 3D-IC redundancy analysis. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) (pp. 335-336). [7401724] (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2015.7401724
Cho, Keewon ; Lee, Woosung ; Kim, Jooyoung ; Kang, Sungho. / Failure bitmap compression method for 3D-IC redundancy analysis. ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., 2016. pp. 335-336 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).
@inproceedings{143924dee29f45898e767cc469743422,
title = "Failure bitmap compression method for 3D-IC redundancy analysis",
abstract = "As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80{\%} of reduction rate in the failure bitmap size.",
author = "Keewon Cho and Woosung Lee and Jooyoung Kim and Sungho Kang",
year = "2016",
month = "2",
day = "8",
doi = "10.1109/ISOCC.2015.7401724",
language = "English",
series = "ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "335--336",
booktitle = "ISOCC 2015 - International SoC Design Conference",
address = "United States",

}

Cho, K, Lee, W, Kim, J & Kang, S 2016, Failure bitmap compression method for 3D-IC redundancy analysis. in ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)., 7401724, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE), Institute of Electrical and Electronics Engineers Inc., pp. 335-336, 12th International SoC Design Conference, ISOCC 2015, Gyeongju, Korea, Republic of, 15/11/2. https://doi.org/10.1109/ISOCC.2015.7401724

Failure bitmap compression method for 3D-IC redundancy analysis. / Cho, Keewon; Lee, Woosung; Kim, Jooyoung; Kang, Sungho.

ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., 2016. p. 335-336 7401724 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Failure bitmap compression method for 3D-IC redundancy analysis

AU - Cho, Keewon

AU - Lee, Woosung

AU - Kim, Jooyoung

AU - Kang, Sungho

PY - 2016/2/8

Y1 - 2016/2/8

N2 - As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

AB - As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

UR - http://www.scopus.com/inward/record.url?scp=84963861086&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84963861086&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2015.7401724

DO - 10.1109/ISOCC.2015.7401724

M3 - Conference contribution

AN - SCOPUS:84963861086

T3 - ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

SP - 335

EP - 336

BT - ISOCC 2015 - International SoC Design Conference

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Cho K, Lee W, Kim J, Kang S. Failure bitmap compression method for 3D-IC redundancy analysis. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc. 2016. p. 335-336. 7401724. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). https://doi.org/10.1109/ISOCC.2015.7401724