Fast area-efficient VLSI adders

Tackdon Han, David A. Carlson

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

In this paper, we study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results we obtain lead to the design of area-time efficient VLSI adders. This is a major goal of our work: to design very low latency addition circuitry that is also area efficient. To this end, we present a new graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, we are able to design VLSI adders having area A = 0(n log n) whose delay time is the lowest possible value, i. e. the fastest possible area-efficient VLSI adder.

Original languageEnglish
Title of host publicationComputer Arithmetic
Subtitle of host publicationVolume I
PublisherWorld Scientific Publishing Co.
Pages83-90
Number of pages8
ISBN (Electronic)9789814651578
ISBN (Print)9789814651561
DOIs
Publication statusPublished - 2015 Jan 1

Fingerprint

Adders
Prefix
Graph Representation
Time delay
Binary
VLSI Design
Delay Time
Graph in graph theory
Latency
Lowest
Trade-offs
Lower bound

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Engineering(all)
  • Mathematics(all)

Cite this

Han, T., & Carlson, D. A. (2015). Fast area-efficient VLSI adders. In Computer Arithmetic: Volume I (pp. 83-90). World Scientific Publishing Co.. https://doi.org/10.1142/9789814651578
Han, Tackdon ; Carlson, David A. / Fast area-efficient VLSI adders. Computer Arithmetic: Volume I. World Scientific Publishing Co., 2015. pp. 83-90
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Han, T & Carlson, DA 2015, Fast area-efficient VLSI adders. in Computer Arithmetic: Volume I. World Scientific Publishing Co., pp. 83-90. https://doi.org/10.1142/9789814651578

Fast area-efficient VLSI adders. / Han, Tackdon; Carlson, David A.

Computer Arithmetic: Volume I. World Scientific Publishing Co., 2015. p. 83-90.

Research output: Chapter in Book/Report/Conference proceedingChapter

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Han T, Carlson DA. Fast area-efficient VLSI adders. In Computer Arithmetic: Volume I. World Scientific Publishing Co. 2015. p. 83-90 https://doi.org/10.1142/9789814651578