FAST AREA-EFFICIENT VLSI ADDERS.

Tackdon Han, David A. Carlson

Research output: Contribution to conferencePaper

193 Citations (Scopus)

Abstract

The authors study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results obtained lead to the design of area-time-efficient VLSI adders. This is a major goal of the work: to design very-low-latency addition circuitry that is also area-efficient. To this end, the authors present a graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the authors are able to design VLSI adders having value, i. e. , the fastest possible area-efficient VLSI adder.

Original languageEnglish
Pages49-56
Number of pages8
Publication statusPublished - 1987 Jan 1

Fingerprint

Adders
Prefix
Graph Representation
Binary
VLSI Design
Graph in graph theory
Latency
Trade-offs
Lower bound
Design

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

Cite this

Han, T., & Carlson, D. A. (1987). FAST AREA-EFFICIENT VLSI ADDERS.. 49-56.
@conference{c6e2846c4995406380b0adc576c0a409,
title = "FAST AREA-EFFICIENT VLSI ADDERS.",
abstract = "The authors study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results obtained lead to the design of area-time-efficient VLSI adders. This is a major goal of the work: to design very-low-latency addition circuitry that is also area-efficient. To this end, the authors present a graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the authors are able to design VLSI adders having value, i. e. , the fastest possible area-efficient VLSI adder.",
author = "Tackdon Han and Carlson, {David A.}",
year = "1987",
month = "1",
day = "1",
language = "English",
pages = "49--56",

}

Han, T & Carlson, DA 1987, 'FAST AREA-EFFICIENT VLSI ADDERS.' pp. 49-56.

FAST AREA-EFFICIENT VLSI ADDERS. / Han, Tackdon; Carlson, David A.

1987. 49-56.

Research output: Contribution to conferencePaper

TY - CONF

T1 - FAST AREA-EFFICIENT VLSI ADDERS.

AU - Han, Tackdon

AU - Carlson, David A.

PY - 1987/1/1

Y1 - 1987/1/1

N2 - The authors study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results obtained lead to the design of area-time-efficient VLSI adders. This is a major goal of the work: to design very-low-latency addition circuitry that is also area-efficient. To this end, the authors present a graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the authors are able to design VLSI adders having value, i. e. , the fastest possible area-efficient VLSI adder.

AB - The authors study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results obtained lead to the design of area-time-efficient VLSI adders. This is a major goal of the work: to design very-low-latency addition circuitry that is also area-efficient. To this end, the authors present a graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the authors are able to design VLSI adders having value, i. e. , the fastest possible area-efficient VLSI adder.

UR - http://www.scopus.com/inward/record.url?scp=0023218636&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023218636&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0023218636

SP - 49

EP - 56

ER -