The authors study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results obtained lead to the design of area-time-efficient VLSI adders. This is a major goal of the work: to design very-low-latency addition circuitry that is also area-efficient. To this end, the authors present a graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the authors are able to design VLSI adders having value, i. e. , the fastest possible area-efficient VLSI adder.
|Number of pages||8|
|Publication status||Published - 1987|
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture