Built-in redundancy analysis (BIRA) is widely used for memory yield improvement. However, increases in fault occurrence probability inevitably lead to the use of various spare lines to achieve a high repair rate. Generally, it is difficult to apply conventional BIRAs for memories with various spare lines because they focus on a simple spare structure. Therefore, this study examines a BIRA that focuses on a various spare lines structure. The proposed BIRA achieves a high repair rate through the use of various spare lines. Although long analysis time is typically required due to the use of various spare lines, the proposed BIRA solves the problem through sequential spare line allocation. Additionally, it achieves hardware overhead reduction through a simple analyzer. These advantages of the proposed BIRA are demonstrated experimentally.
|Number of pages||10|
|Journal||IEEE Transactions on Reliability|
|Publication status||Published - 2018 Mar|
Bibliographical noteFunding Information:
Manuscript received May 23, 2017; revised September 15, 2017 and October 11, 2017; accepted November 24, 2017. Date of publication January 9, 2018; date of current version March 1, 2018. This research was supported by the MOTIE (Ministry of Trade, Industry & Energy (10052875) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Associate Editor: W.-T. Chien. (Corresponding author: Sungho Kang.) H. Lee, K. Cho, and S. Kang are with the Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: firstname.lastname@example.org; email@example.com; firstname.lastname@example.org).
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering