Abstract
Content addressable memory (CAM) is a key component to build the tag memory of a highly associative cache. As CMOS process technology scales,soft error rates (SER) in CAM cells increase significantly. Bit flipping in CAM cell leads to a false miss upon a cache access, which could be fatal from a system point of view. Previous schemes either focused on reducing the probability of soft errors or had an unbounded single soft error correction time. Compared with previous schemes, our approach completely detects and corrects multiple soft errors. The detection and correction in our scheme happens as a background process, does not interfere with concurrent cache accesses, and does not affect the performance of time-critical cache operations. In addition, we enhance the cache miss holding register structure of a non-blocking cache to avoid data corruption due to any false cache miss happening between occurrence and correction of errors.
| Original language | English |
|---|---|
| Title of host publication | Computer Applications for Security, Control and System Engineering - International Conferences, SecTech, CA, CES3 2012, Held in Conjunction with GST 2012, Proceedings |
| Pages | 424-431 |
| Number of pages | 8 |
| DOIs | |
| Publication status | Published - 2012 Nov 29 |
| Event | 2012 Int. Conf. on SecTech 2012, 2012 Int. Conf. on Control and Automation, CA 2012 and the 2012 Int. Conf. on Circuits, Control, Communication, Electricity, Electronics, Energy, System, Signal and Simulation, Held in Conjunction with GST 2012 - Jeju Island, Korea, Republic of Duration: 2012 Nov 28 → 2012 Dec 2 |
Publication series
| Name | Communications in Computer and Information Science |
|---|---|
| Volume | 339 CCIS |
| ISSN (Print) | 1865-0929 |
Other
| Other | 2012 Int. Conf. on SecTech 2012, 2012 Int. Conf. on Control and Automation, CA 2012 and the 2012 Int. Conf. on Circuits, Control, Communication, Electricity, Electronics, Energy, System, Signal and Simulation, Held in Conjunction with GST 2012 |
|---|---|
| Country | Korea, Republic of |
| City | Jeju Island |
| Period | 12/11/28 → 12/12/2 |
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All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Mathematics(all)
Cite this
}
Fast correction of multiple soft errors in highly associative cache with CAM-based tag. / Lee, Hyuk Jun; Kim, Seung Cheol; Chung, Eui Young.
Computer Applications for Security, Control and System Engineering - International Conferences, SecTech, CA, CES3 2012, Held in Conjunction with GST 2012, Proceedings. 2012. p. 424-431 (Communications in Computer and Information Science; Vol. 339 CCIS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Fast correction of multiple soft errors in highly associative cache with CAM-based tag
AU - Lee, Hyuk Jun
AU - Kim, Seung Cheol
AU - Chung, Eui Young
PY - 2012/11/29
Y1 - 2012/11/29
N2 - Content addressable memory (CAM) is a key component to build the tag memory of a highly associative cache. As CMOS process technology scales,soft error rates (SER) in CAM cells increase significantly. Bit flipping in CAM cell leads to a false miss upon a cache access, which could be fatal from a system point of view. Previous schemes either focused on reducing the probability of soft errors or had an unbounded single soft error correction time. Compared with previous schemes, our approach completely detects and corrects multiple soft errors. The detection and correction in our scheme happens as a background process, does not interfere with concurrent cache accesses, and does not affect the performance of time-critical cache operations. In addition, we enhance the cache miss holding register structure of a non-blocking cache to avoid data corruption due to any false cache miss happening between occurrence and correction of errors.
AB - Content addressable memory (CAM) is a key component to build the tag memory of a highly associative cache. As CMOS process technology scales,soft error rates (SER) in CAM cells increase significantly. Bit flipping in CAM cell leads to a false miss upon a cache access, which could be fatal from a system point of view. Previous schemes either focused on reducing the probability of soft errors or had an unbounded single soft error correction time. Compared with previous schemes, our approach completely detects and corrects multiple soft errors. The detection and correction in our scheme happens as a background process, does not interfere with concurrent cache accesses, and does not affect the performance of time-critical cache operations. In addition, we enhance the cache miss holding register structure of a non-blocking cache to avoid data corruption due to any false cache miss happening between occurrence and correction of errors.
UR - http://www.scopus.com/inward/record.url?scp=84869781846&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84869781846&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-35264-5_57
DO - 10.1007/978-3-642-35264-5_57
M3 - Conference contribution
AN - SCOPUS:84869781846
SN - 9783642352638
T3 - Communications in Computer and Information Science
SP - 424
EP - 431
BT - Computer Applications for Security, Control and System Engineering - International Conferences, SecTech, CA, CES3 2012, Held in Conjunction with GST 2012, Proceedings
ER -