Fast exploration of parameterized bus architecture for communication- centric SoC design

Chulho Shin, Young Taek Kim, Eui-Young Chung, Kyu Myung Choi, Jeong Taek Kong, Soo Kwan Eo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.

Original languageEnglish
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
EditorsG. Gielen, J. Figueras
Pages352-357
Number of pages6
Publication statusPublished - 2004 Jul 12
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: 2004 Feb 162004 Feb 20

Publication series

NameProceedings - Design, Automation and Test in Europe Conference and Exhibition
Volume1

Other

OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
CountryFrance
CityParis
Period04/2/1604/2/20

Fingerprint

Communication
Genetic algorithms
System-on-chip

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Shin, C., Kim, Y. T., Chung, E-Y., Choi, K. M., Kong, J. T., & Eo, S. K. (2004). Fast exploration of parameterized bus architecture for communication- centric SoC design. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 (pp. 352-357). (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 1).
Shin, Chulho ; Kim, Young Taek ; Chung, Eui-Young ; Choi, Kyu Myung ; Kong, Jeong Taek ; Eo, Soo Kwan. / Fast exploration of parameterized bus architecture for communication- centric SoC design. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. editor / G. Gielen ; J. Figueras. 2004. pp. 352-357 (Proceedings - Design, Automation and Test in Europe Conference and Exhibition).
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Shin, C, Kim, YT, Chung, E-Y, Choi, KM, Kong, JT & Eo, SK 2004, Fast exploration of parameterized bus architecture for communication- centric SoC design. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 352-357, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, France, 04/2/16.

Fast exploration of parameterized bus architecture for communication- centric SoC design. / Shin, Chulho; Kim, Young Taek; Chung, Eui-Young; Choi, Kyu Myung; Kong, Jeong Taek; Eo, Soo Kwan.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. ed. / G. Gielen; J. Figueras. 2004. p. 352-357 (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Shin C, Kim YT, Chung E-Y, Choi KM, Kong JT, Eo SK. Fast exploration of parameterized bus architecture for communication- centric SoC design. In Gielen G, Figueras J, editors, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. 2004. p. 352-357. (Proceedings - Design, Automation and Test in Europe Conference and Exhibition).