Abstract
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 |
| Editors | G. Gielen, J. Figueras |
| Pages | 352-357 |
| Number of pages | 6 |
| Publication status | Published - 2004 Jul 12 |
| Event | Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France Duration: 2004 Feb 16 → 2004 Feb 20 |
Publication series
| Name | Proceedings - Design, Automation and Test in Europe Conference and Exhibition |
|---|---|
| Volume | 1 |
Other
| Other | Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 |
|---|---|
| Country | France |
| City | Paris |
| Period | 04/2/16 → 04/2/20 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
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Fast exploration of parameterized bus architecture for communication- centric SoC design. / Shin, Chulho; Kim, Young Taek; Chung, Eui-Young; Choi, Kyu Myung; Kong, Jeong Taek; Eo, Soo Kwan.
Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. ed. / G. Gielen; J. Figueras. 2004. p. 352-357 (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 1).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Fast exploration of parameterized bus architecture for communication- centric SoC design
AU - Shin, Chulho
AU - Kim, Young Taek
AU - Chung, Eui-Young
AU - Choi, Kyu Myung
AU - Kong, Jeong Taek
AU - Eo, Soo Kwan
PY - 2004/7/12
Y1 - 2004/7/12
N2 - For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.
AB - For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.
UR - http://www.scopus.com/inward/record.url?scp=3042613682&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=3042613682&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:3042613682
SN - 0769520855
SN - 9780769520858
T3 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition
SP - 352
EP - 357
BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
A2 - Gielen, G.
A2 - Figueras, J.
ER -