Fast floating-point normalisation unit realised using NOR planes

Kyung Nam Han, Sang Wook Han, Euisik Yoon

Research output: Contribution to journal › Article

Abstract

A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.

Original languageEnglish
Pages (from-to)857-858
Number of pages2
JournalElectronics Letters
Volume38
Issue number16
DOIs
Publication statusPublished - 2002 Aug 1

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Merging
Metals

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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Han, Kyung Nam ; Han, Sang Wook ; Yoon, Euisik. / Fast floating-point normalisation unit realised using NOR planes. In: Electronics Letters. 2002 ; Vol. 38, No. 16. pp. 857-858.
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Han, KN, Han, SW & Yoon, E 2002, 'Fast floating-point normalisation unit realised using NOR planes', Electronics Letters, vol. 38, no. 16, pp. 857-858. https://doi.org/10.1049/el:20020555

Fast floating-point normalisation unit realised using NOR planes. / Han, Kyung Nam; Han, Sang Wook; Yoon, Euisik.

In: Electronics Letters, Vol. 38, No. 16, 01.08.2002, p. 857-858.

Research output: Contribution to journal › Article

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Han KN, Han SW, Yoon E. Fast floating-point normalisation unit realised using NOR planes. Electronics Letters. 2002 Aug 1;38(16):857-858. https://doi.org/10.1049/el:20020555

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