Fast floating-point normalisation unit realised using NOR planes

Kyung Nam Han, Sang Wook Han, Euisik Yoon

Research output: Contribution to journalArticle

Abstract

A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.

Original languageEnglish
Pages (from-to)857-858
Number of pages2
JournalElectronics Letters
Volume38
Issue number16
DOIs
Publication statusPublished - 2002 Aug 1

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Merging
Metals

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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Han, Kyung Nam ; Han, Sang Wook ; Yoon, Euisik. / Fast floating-point normalisation unit realised using NOR planes. In: Electronics Letters. 2002 ; Vol. 38, No. 16. pp. 857-858.
@article{9bd6eae0b4ae4a2a833e06f6d7f4756e,
title = "Fast floating-point normalisation unit realised using NOR planes",
abstract = "A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.",
author = "Han, {Kyung Nam} and Han, {Sang Wook} and Euisik Yoon",
year = "2002",
month = "8",
day = "1",
doi = "10.1049/el:20020555",
language = "English",
volume = "38",
pages = "857--858",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "16",

}

Fast floating-point normalisation unit realised using NOR planes. / Han, Kyung Nam; Han, Sang Wook; Yoon, Euisik.

In: Electronics Letters, Vol. 38, No. 16, 01.08.2002, p. 857-858.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Fast floating-point normalisation unit realised using NOR planes

AU - Han, Kyung Nam

AU - Han, Sang Wook

AU - Yoon, Euisik

PY - 2002/8/1

Y1 - 2002/8/1

N2 - A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.

AB - A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.

UR - http://www.scopus.com/inward/record.url?scp=0036683794&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036683794&partnerID=8YFLogxK

U2 - 10.1049/el:20020555

DO - 10.1049/el:20020555

M3 - Article

AN - SCOPUS:0036683794

VL - 38

SP - 857

EP - 858

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 16

ER -