Abstract
A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.
| Original language | English |
|---|---|
| Pages (from-to) | 857-858 |
| Number of pages | 2 |
| Journal | Electronics Letters |
| Volume | 38 |
| Issue number | 16 |
| DOIs | |
| Publication status | Published - 2002 Aug 1 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Cite this
Han, K. N., Han, S. W., & Yoon, E. (2002). Fast floating-point normalisation unit realised using NOR planes. Electronics Letters, 38(16), 857-858. https://doi.org/10.1049/el:20020555