FlashGPU: Placing new flash next to GPU cores

Jie Zhang; Miryeong Kwon; Hyojong Kim; Hyesoon Kim; Myoungsoo Jung

doi:10.1145/3316781.3317827

FlashGPU: Placing new flash next to GPU cores

Jie Zhang, Miryeong Kwon, Hyojong Kim, Hyesoon Kim, Myoungsoo Jung

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

We propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.

Original language	English
Title of host publication	Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450367257
DOIs	https://doi.org/10.1145/3316781.3317827
Publication status	Published - 2019 Jun 2
Event	56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States Duration: 2019 Jun 2 → 2019 Jun 6

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	56th Annual Design Automation Conference, DAC 2019
Country/Territory	United States
City	Las Vegas
Period	19/6/2 → 19/6/6

Bibliographical note

Funding Information:
This research is mainly supported by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, IITP-2018-2017-0-01015, NRF 2015M3C4A7065645, NRF-2017R1A4A1015498 and MemRay grant. The authors thank Samsung for its Z-SSD sample donations.

Publisher Copyright:
© 2019 Association for Computing Machinery.

All Science Journal Classification (ASJC) codes

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1145/3316781.3317827

Cite this

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title = "FlashGPU: Placing new flash next to GPU cores",

abstract = "We propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.",

author = "Jie Zhang and Miryeong Kwon and Hyojong Kim and Hyesoon Kim and Myoungsoo Jung",

note = "Funding Information: This research is mainly supported by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, IITP-2018-2017-0-01015, NRF 2015M3C4A7065645, NRF-2017R1A4A1015498 and MemRay grant. The authors thank Samsung for its Z-SSD sample donations. Publisher Copyright: {\textcopyright} 2019 Association for Computing Machinery.; 56th Annual Design Automation Conference, DAC 2019 ; Conference date: 02-06-2019 Through 06-06-2019",

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doi = "10.1145/3316781.3317827",

language = "English",

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Zhang, J, Kwon, M, Kim, H, Kim, H & Jung, M 2019, FlashGPU: Placing new flash next to GPU cores. in Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019., a156, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., 56th Annual Design Automation Conference, DAC 2019, Las Vegas, United States, 19/6/2. https://doi.org/10.1145/3316781.3317827

FlashGPU : Placing new flash next to GPU cores. / Zhang, Jie; Kwon, Miryeong; Kim, Hyojong et al.

Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. a156 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Jung, Myoungsoo

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AB - We propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.

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M3 - Conference contribution

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FlashGPU: Placing new flash next to GPU cores

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

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