Abstract
We propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781450367257 |
| DOIs | |
| Publication status | Published - 2019 Jun 2 |
| Event | 56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States Duration: 2019 Jun 2 → 2019 Jun 6 |
Publication series
| Name | Proceedings - Design Automation Conference |
|---|---|
| ISSN (Print) | 0738-100X |
Conference
| Conference | 56th Annual Design Automation Conference, DAC 2019 |
|---|---|
| Country | United States |
| City | Las Vegas |
| Period | 19/6/2 → 19/6/6 |
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All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modelling and Simulation
Cite this
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FlashGPU : Placing new flash next to GPU cores. / Zhang, Jie; Kwon, Miryeong; Kim, Hyojong; Kim, Hyesoon; Jung, Myoungsoo.
Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. a156 (Proceedings - Design Automation Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - FlashGPU
T2 - Placing new flash next to GPU cores
AU - Zhang, Jie
AU - Kwon, Miryeong
AU - Kim, Hyojong
AU - Kim, Hyesoon
AU - Jung, Myoungsoo
PY - 2019/6/2
Y1 - 2019/6/2
N2 - We propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.
AB - We propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.
UR - http://www.scopus.com/inward/record.url?scp=85067831721&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85067831721&partnerID=8YFLogxK
U2 - 10.1145/3316781.3317827
DO - 10.1145/3316781.3317827
M3 - Conference contribution
AN - SCOPUS:85067831721
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
ER -