To understand how the human brain works, neuroscientists heavily rely on brain simulations which incorporate the concept of time to their operating model. In the simulations, neurons transmit their signals through synapses whose weights change over time and by the activity of the associated neurons. Such changes in synaptic weights, known as learning, are thought to contribute to memory, and various learning rules exist to model different behaviors of the human brain. Due to the diverse neurons and learning rules, neuroscientists perform the simulations using highly programmable general-purpose processors. Unfortunately, the processors greatly suffer from the high computational overheads of the learning rules. As an alternative, brain simulation accelerators achieve orders ofmagnitude higher performance; however, they have limited flexibility and cannot support the diverse neurons and learning rules. In this paper, we present FlexLearn, a flexible on-chip learning engine to enable fast and highly efficient brain simulations. FlexLearn achieves high flexibility by supporting diverse biologically plausible sub-rules which can be combined to simulate various target learning rules. To design FlexLearn, we first identify 17 representative sub-rules which adjust the synaptic weights in different manners. Then, we design and compact the specialized datapaths for the subrules and identify dependencies between them to maximize parallelism. After that, we present an example flexible brain simulation processor by integrating the datapaths with the state-of-the-art flexibledigital neuron and existing accelerator to support end-to-end simulations. Our evaluation using a 45-nm cell library shows that the 128-core brain simulation processor prototype with FlexLearn greatly improves the harmonic mean per-area performance and the energy efficiency by 30.07 and 126.87, respectively, over the server-class CPU. The prototype also achieves the harmonic mean per-area speedup of 1.41 over the current state-of-the-art 128-core accelerator which supports programmable learning rules.
|Title of host publication||MICRO 2019 - 52nd Annual IEEE/ACM International Symposium on Microarchitecture, Proceedings|
|Publisher||IEEE Computer Society|
|Number of pages||15|
|Publication status||Published - 2019 Oct 12|
|Event||52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019 - Columbus, United States|
Duration: 2019 Oct 12 → 2019 Oct 16
|Name||Proceedings of the Annual International Symposium on Microarchitecture, MICRO|
|Conference||52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019|
|Period||19/10/12 → 19/10/16|
Bibliographical noteFunding Information:
This work was partly supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (NRF-2015M3C4A7065647, NRF2017R1A2B3011038, NRF-2019-Global Ph.D. Fellowship Program), Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No.1711080972), and Creative Pioneering Researchers Program through Seoul National University. We also appreciate the support from Samsung Advanced Institute of Technology (SAIT), and Automation and Systems Research Institute (ASRI), Inter-university Semiconductor Research Center (ISRC) at Seoul National University.
© 2019 Association for Computing Machinery.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture