Phase change memory (PCM) is a scalable, non-volatile emerging memory. The storage density of the PCM can be enhanced by using the multi-level cell (MLC) operation. However, the MLC PCM suffers from low reliability due to resistance drift. The rate of resistance drift is proportional to the initial resistance of the cell with intermediate storage levels being particularly vulnerable. Using heavy Error Correction Codes (ECC) results in poor effective storage density (data bits per cell) of the MLC PCM. The state-of-the-art Tri-level cell technique improves reliability by using only three out of four storage levels, thus eliminating the ECC overhead. However, its storage density is much less than the ideal MLC PCM. Moreover, its storage density is fixed even if practically the MLC PCM reliability is improved. This paper introduces a more flexible pattern redistribution technique, Flipcy, to improve the MLC PCM reliability and effective storage density. The proposed method proportions the data-patterns according to the rate of resistance drift for different storage levels. A simple flip or a complement operation is used to reduce the percentage of the most error-prone pattern. The simulation results show up to 107X reduction in the error rate and 31% improvement in performance compared to the conventional MLC PCM. With a reduced overhead of the auxiliary bits and ECC parity bits, the proposed method can achieve about 25% improvement in effective storage density over the Tri-level cell approach for a similar level of reliability while incurring about 11% degradation in performance compared to the Tri-level cell approach. This performance degradation can be reduced when the proposed method is accompanied with orthogonal techniques to improve MLC PCM reliability and efficient scrubbing methods.