The quadruple-level cell technology is demonstrated in an Au/Al2O3/HfO2/TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five-bits-per-cell technology, which can hardly be imagined in NAND flash, whose state-of-the-art multiple-cell technology is only at three-level (eight states) to this day.
|Publication status||Published - 2017 Oct 25|
Bibliographical noteFunding Information:
G.H.K. and H.J. contributed equally to this work. The financial support obtained from the Development of Organometallics and Device Fabrication for IT-ET Convergence Project through the Korea Research Institute of Chemical Technology (KRICT) of the Republic of Korea (SI1703-02) is acknowledged. C.S.H. acknowledges the support from the Global Research Laboratory Program (2012K1A1A2040157) of the National Research Foundation of Korea (NRF). H.J. appreciates the financial support from the KIST Institution Program (Program 2E27160).
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All Science Journal Classification (ASJC) codes
- Materials Science(all)