FRESH: A New Test Result Extraction Scheme for Fast TSV Tests

Jaeseok Park, Hyunyul Lim, Sungho Kang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments.

Original languageEnglish
Article number7488276
Pages (from-to)336-345
Number of pages10
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume36
Issue number2
DOIs
Publication statusPublished - 2017 Feb 1

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Silicon
Redundancy
Hardware
Fabrication
Testing

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

@article{b8aa80f8705e4c42b39d32f17dfa0a16,
title = "FRESH: A New Test Result Extraction Scheme for Fast TSV Tests",
abstract = "Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments.",
author = "Jaeseok Park and Hyunyul Lim and Sungho Kang",
year = "2017",
month = "2",
day = "1",
doi = "10.1109/TCAD.2016.2578883",
language = "English",
volume = "36",
pages = "336--345",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

FRESH : A New Test Result Extraction Scheme for Fast TSV Tests. / Park, Jaeseok; Lim, Hyunyul; Kang, Sungho.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 2, 7488276, 01.02.2017, p. 336-345.

Research output: Contribution to journalArticle

TY - JOUR

T1 - FRESH

T2 - A New Test Result Extraction Scheme for Fast TSV Tests

AU - Park, Jaeseok

AU - Lim, Hyunyul

AU - Kang, Sungho

PY - 2017/2/1

Y1 - 2017/2/1

N2 - Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments.

AB - Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments.

UR - http://www.scopus.com/inward/record.url?scp=85010378586&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85010378586&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2016.2578883

DO - 10.1109/TCAD.2016.2578883

M3 - Article

AN - SCOPUS:85010378586

VL - 36

SP - 336

EP - 345

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 2

M1 - 7488276

ER -