In this work, we propose FUSE, a novel GPU cache system that integrates spin-transfer torque magnetic random-access memory (STT-MRAM) into the on-chip L1D cache. FUSE can minimize the number of outgoing memory accesses over the interconnection network of GPU's multiprocessors, which in turn can considerably improve the level of massive computing parallelism in GPUs. Specifically, FUSE predicts a read-level of GPU memory accesses by extracting GPU runtime information and places write-once-read-multiple (WORM) data blocks into the STT-MRAM, while accommodating write-multiple data blocks over a small portion of SRAM in the L1D cache. To further reduce the off-chip memory accesses, FUSE also allows WORM data blocks to be allocated anywhere in the STT-MRAM by approximating the associativity with the limited number of tag comparators and I/O peripherals. Our evaluation results show that, in comparison to a traditional GPU cache, our proposed heterogeneous cache reduces the number of outgoing memory references by 32% across the interconnection network, thereby improving the overall performance by 217% and reducing energy cost by 53%.
|Title of host publication||Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||14|
|Publication status||Published - 2019 Mar 26|
|Event||25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019 - Washington, United States|
Duration: 2019 Feb 16 → 2019 Feb 20
|Name||Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019|
|Conference||25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019|
|Period||19/2/16 → 19/2/20|
Bibliographical noteFunding Information:
This research is mainly supported by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, IITP-2018-2017-0-01015, NRF 2015M3C4A7065645, Yonsei Future Research Grant (2017-22-0105) and MemRay grant (2015-11-1731). M. Kandemir is supported in part by grants by NSF grants 1822923, 1439021, 1629915, 1626251, 1629129, 1763681, 1526750 and 1439057. Myoungsoo Jung is the corresponding author who has ownership of this work.
© 2019 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications