Gate insulator inhomogeneity in thin film transistors having a polycrystalline silicon layer prepared directly by catalytic chemical vapor deposition at a low temperature

Hyun Jun Cho, Wan Shick Hong, Sung Hyun Lee, Tae Hwan Kim, Kyung Min Lee, Kyung Bae Park, Ji Sim Jung, Jang Yeon Kwon

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Polycrystalline silicon (poly-Si) films were prepared directly at a low temperature (<200°C) by using catalytic chemical vapor deposition (Cat-CVD) technique without subsequent crystallization steps. Top-gate coplanar type thin-film transistors were fabricated using the as-deposited poly-Si films. We obtained a high mobility of ∼40 cm2/(V s) and a subthreshold slope of 0.54 V/decade. Instability in threshold voltage with the drain bias could be suppressed by improving the homogeneity in the gate insulator.

Original languageEnglish
Pages (from-to)L1228-L1230
JournalJapanese Journal of Applied Physics, Part 2: Letters
Volume46
Issue number45-49
DOIs
Publication statusPublished - 2007 Dec 14

Fingerprint

Thin film transistors
silicon films
Polysilicon
Chemical vapor deposition
inhomogeneity
transistors
insulators
vapor deposition
silicon
thin films
Threshold voltage
threshold voltage
homogeneity
Crystallization
crystallization
slopes
Temperature

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy (miscellaneous)
  • Physics and Astronomy(all)

Cite this

Cho, Hyun Jun ; Hong, Wan Shick ; Lee, Sung Hyun ; Kim, Tae Hwan ; Lee, Kyung Min ; Park, Kyung Bae ; Jung, Ji Sim ; Kwon, Jang Yeon. / Gate insulator inhomogeneity in thin film transistors having a polycrystalline silicon layer prepared directly by catalytic chemical vapor deposition at a low temperature. In: Japanese Journal of Applied Physics, Part 2: Letters. 2007 ; Vol. 46, No. 45-49. pp. L1228-L1230.
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Gate insulator inhomogeneity in thin film transistors having a polycrystalline silicon layer prepared directly by catalytic chemical vapor deposition at a low temperature. / Cho, Hyun Jun; Hong, Wan Shick; Lee, Sung Hyun; Kim, Tae Hwan; Lee, Kyung Min; Park, Kyung Bae; Jung, Ji Sim; Kwon, Jang Yeon.

In: Japanese Journal of Applied Physics, Part 2: Letters, Vol. 46, No. 45-49, 14.12.2007, p. L1228-L1230.

Research output: Contribution to journalArticle

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T1 - Gate insulator inhomogeneity in thin film transistors having a polycrystalline silicon layer prepared directly by catalytic chemical vapor deposition at a low temperature

AU - Cho, Hyun Jun

AU - Hong, Wan Shick

AU - Lee, Sung Hyun

AU - Kim, Tae Hwan

AU - Lee, Kyung Min

AU - Park, Kyung Bae

AU - Jung, Ji Sim

AU - Kwon, Jang Yeon

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AB - Polycrystalline silicon (poly-Si) films were prepared directly at a low temperature (<200°C) by using catalytic chemical vapor deposition (Cat-CVD) technique without subsequent crystallization steps. Top-gate coplanar type thin-film transistors were fabricated using the as-deposited poly-Si films. We obtained a high mobility of ∼40 cm2/(V s) and a subthreshold slope of 0.54 V/decade. Instability in threshold voltage with the drain bias could be suppressed by improving the homogeneity in the gate insulator.

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