Gate stack technology for nanoscale devices

Byoung Hun Lee, Jungwoo Oh, Hsing Huang Tseng, Rajarao Jammy, Howard Huff

Research output: Contribution to journalArticlepeer-review

173 Citations (Scopus)


Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

Original languageEnglish
Pages (from-to)32-40
Number of pages9
JournalMaterials Today
Issue number6
Publication statusPublished - 2006 Jun

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering


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