Gate stack technology for nanoscale devices

Byoung Hun Lee, Jungwoo Oh, Hsing Huang Tseng, Rajarao Jammy, Howard Huff

Research output: Contribution to journalArticle

153 Citations (Scopus)

Abstract

Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

Original languageEnglish
Pages (from-to)32-40
Number of pages9
JournalMaterials Today
Volume9
Issue number6
DOIs
Publication statusPublished - 2006 Jun 1

Fingerprint

MOS devices
Gate dielectrics
MOSFET devices
Permittivity
CMOS
scaling
semiconductor devices
field effect transistors
permittivity

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

Lee, Byoung Hun ; Oh, Jungwoo ; Tseng, Hsing Huang ; Jammy, Rajarao ; Huff, Howard. / Gate stack technology for nanoscale devices. In: Materials Today. 2006 ; Vol. 9, No. 6. pp. 32-40.
@article{3558b4b7fc8c4676a2ede457975e3684,
title = "Gate stack technology for nanoscale devices",
abstract = "Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.",
author = "Lee, {Byoung Hun} and Jungwoo Oh and Tseng, {Hsing Huang} and Rajarao Jammy and Howard Huff",
year = "2006",
month = "6",
day = "1",
doi = "10.1016/S1369-7021(06)71541-3",
language = "English",
volume = "9",
pages = "32--40",
journal = "Materials Today",
issn = "1369-7021",
publisher = "Elsevier",
number = "6",

}

Lee, BH, Oh, J, Tseng, HH, Jammy, R & Huff, H 2006, 'Gate stack technology for nanoscale devices', Materials Today, vol. 9, no. 6, pp. 32-40. https://doi.org/10.1016/S1369-7021(06)71541-3

Gate stack technology for nanoscale devices. / Lee, Byoung Hun; Oh, Jungwoo; Tseng, Hsing Huang; Jammy, Rajarao; Huff, Howard.

In: Materials Today, Vol. 9, No. 6, 01.06.2006, p. 32-40.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Gate stack technology for nanoscale devices

AU - Lee, Byoung Hun

AU - Oh, Jungwoo

AU - Tseng, Hsing Huang

AU - Jammy, Rajarao

AU - Huff, Howard

PY - 2006/6/1

Y1 - 2006/6/1

N2 - Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

AB - Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

UR - http://www.scopus.com/inward/record.url?scp=33646875269&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646875269&partnerID=8YFLogxK

U2 - 10.1016/S1369-7021(06)71541-3

DO - 10.1016/S1369-7021(06)71541-3

M3 - Article

AN - SCOPUS:33646875269

VL - 9

SP - 32

EP - 40

JO - Materials Today

JF - Materials Today

SN - 1369-7021

IS - 6

ER -