General purpose discrete-time multiplexing neuron-array architecture

Gunhee Han, Edgar Sanchez-Sinencio

Research output: Contribution to journalConference article

Abstract

The main difficulties in neural network (NN) hardware implementations are the massive connections and problem oriented topology. It is proposed an efficient general purpose discrete-time multiplexing neuron array (MNA) to deal with these problems. A versatile precise multiplier is presented. The proposed MNA can configurate various neural topologies and the size of networks can be easily augmented. The implementations of Multi-Layer Perceptron (MLP), Fully-Connected Recurrent (FCR) and Bidirectional Associated Memory (BAM) are considered as applications of the MNA. The MNA can be applied to any type of discrete-time circuit implementation. The basic building blocks are implemented with multipliers and switched-capacitor integrators. Experimental IC building blocks results are in good agreement with theoretical results.

Original languageEnglish
Pages (from-to)1320-1323
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
Publication statusPublished - 1995 Jan 1
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 1995 Apr 301995 May 3

Fingerprint

Multiplexing
Neurons
Topology
Multilayer neural networks
Capacitors
Neural networks
Hardware
Data storage equipment
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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General purpose discrete-time multiplexing neuron-array architecture. / Han, Gunhee; Sanchez-Sinencio, Edgar.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 01.01.1995, p. 1320-1323.

Research output: Contribution to journalConference article

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