Abstract
The main difficulties in neural network (NN) hardware implementations are the massive connections and problem oriented topology. It is proposed an efficient general purpose discrete-time multiplexing neuron array (MNA) to deal with these problems. A versatile precise multiplier is presented. The proposed MNA can configurate various neural topologies and the size of networks can be easily augmented. The implementations of Multi-Layer Perceptron (MLP), Fully-Connected Recurrent (FCR) and Bidirectional Associated Memory (BAM) are considered as applications of the MNA. The MNA can be applied to any type of discrete-time circuit implementation. The basic building blocks are implemented with multipliers and switched-capacitor integrators. Experimental IC building blocks results are in good agreement with theoretical results.
| Original language | English |
|---|---|
| Pages (from-to) | 1320-1323 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| Publication status | Published - 1995 Jan 1 |
| Event | Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: 1995 Apr 30 → 1995 May 3 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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General purpose discrete-time multiplexing neuron-array architecture. / Han, Gunhee; Sanchez-Sinencio, Edgar.
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 01.01.1995, p. 1320-1323.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - General purpose discrete-time multiplexing neuron-array architecture
AU - Han, Gunhee
AU - Sanchez-Sinencio, Edgar
PY - 1995/1/1
Y1 - 1995/1/1
N2 - The main difficulties in neural network (NN) hardware implementations are the massive connections and problem oriented topology. It is proposed an efficient general purpose discrete-time multiplexing neuron array (MNA) to deal with these problems. A versatile precise multiplier is presented. The proposed MNA can configurate various neural topologies and the size of networks can be easily augmented. The implementations of Multi-Layer Perceptron (MLP), Fully-Connected Recurrent (FCR) and Bidirectional Associated Memory (BAM) are considered as applications of the MNA. The MNA can be applied to any type of discrete-time circuit implementation. The basic building blocks are implemented with multipliers and switched-capacitor integrators. Experimental IC building blocks results are in good agreement with theoretical results.
AB - The main difficulties in neural network (NN) hardware implementations are the massive connections and problem oriented topology. It is proposed an efficient general purpose discrete-time multiplexing neuron array (MNA) to deal with these problems. A versatile precise multiplier is presented. The proposed MNA can configurate various neural topologies and the size of networks can be easily augmented. The implementations of Multi-Layer Perceptron (MLP), Fully-Connected Recurrent (FCR) and Bidirectional Associated Memory (BAM) are considered as applications of the MNA. The MNA can be applied to any type of discrete-time circuit implementation. The basic building blocks are implemented with multipliers and switched-capacitor integrators. Experimental IC building blocks results are in good agreement with theoretical results.
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M3 - Conference article
AN - SCOPUS:0029191449
VL - 2
SP - 1320
EP - 1323
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
ER -