The main difficulties in neural network (NN) hardware implementations are the massive connections and problem oriented topology. It is proposed an efficient general purpose discrete-time multiplexing neuron array (MNA) to deal with these problems. A versatile precise multiplier is presented. The proposed MNA can configurate various neural topologies and the size of networks can be easily augmented. The implementations of Multi-Layer Perceptron (MLP), Fully-Connected Recurrent (FCR) and Bidirectional Associated Memory (BAM) are considered as applications of the MNA. The MNA can be applied to any type of discrete-time circuit implementation. The basic building blocks are implemented with multipliers and switched-capacitor integrators. Experimental IC building blocks results are in good agreement with theoretical results.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1995 Jan 1|
|Event||Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA|
Duration: 1995 Apr 30 → 1995 May 3
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering