General purpose neuro-image processor architecture

Gunhee Han, Edgar Sanchez-Sinencio

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

A general purpose neuro-image processor architecture based on the Multiplexing Neuron Array(MNA) is proposed. It is a pseudo parallel matrix-vector multiplier. The proposed architecture can process not only vector signals but two dimensional signals as well, so various types of neural networks or image processing paradigm can be implemented without any hardware modification. The major advantage is an unlimited expansion capability due to simple routings between processing elements. The architecture can be implemented with any discrete-time system, i.e., digital system, Switched-Capacitor, Switched-Current. For illustration, a multilayer perceptron network and a recurrent network are implemented with fabricated Switched-Capacitor CMOS chips.

Original languageEnglish
Pages (from-to)495-498
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
Publication statusPublished - 1996 Jan 1
EventProceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
Duration: 1996 May 121996 May 15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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