GPU-Based Redundancy Analysis Using Concurrent Evaluation

Tae Hyun Kim; Hayoung Lee; Sungho Kang

doi:10.1109/TVLSI.2019.2954549

GPU-Based Redundancy Analysis Using Concurrent Evaluation

Tae Hyun Kim, Hayoung Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

Redundancy analysis (RA) is essential for improving memory yield. The recent increase in memory size has made RA more complicated. This article presents graphics processing unit (GPU)-based RA using concurrent evaluation (GRACE), which is an efficient RA technique. In GRACE, to perform dynamic RA, memory faults found during the test are directly analyzed instead of being stored in the fault bitmap in the automatic test equipment (ATE). Therefore, RA is performed simultaneously with the memory test, and the RA latency is eliminated after the test time. Using the GPU, all possible repair cases are examined in parallel; thus, a high memory repair rate is achieved in a short period of time. Also, GRACE can be applied to practical environments where the structure of memory redundancy is complicated. Experimental results indicate that GRACE is faster than other ATE-based RA methods since it completes the RA almost simultaneously at the end of the test. Additionally, the repair rate of GRACE is always higher than those of the other RA methods.

Original language	English
Article number	8935214
Pages (from-to)	805-817
Number of pages	13
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	28
Issue number	3
DOIs	https://doi.org/10.1109/TVLSI.2019.2954549
Publication status	Published - 2020 Mar

Bibliographical note

Funding Information:
Manuscript received July 20, 2019; revised October 18, 2019; accepted November 12, 2019. Date of publication December 17, 2019; date of current version February 25, 2020. This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea Government (Ministry of Science and ICT) (No. 2019R1A2C3011079). (Corresponding author: Sungho Kang.) The authors are with the Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: incendio9@soc.yonsei.ac.kr; yseehy214@soc.yonsei.ac.kr; shkang@yonsei.ac.kr). Digital Object Identifier 10.1109/TVLSI.2019.2954549

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2019.2954549

Cite this

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abstract = "Redundancy analysis (RA) is essential for improving memory yield. The recent increase in memory size has made RA more complicated. This article presents graphics processing unit (GPU)-based RA using concurrent evaluation (GRACE), which is an efficient RA technique. In GRACE, to perform dynamic RA, memory faults found during the test are directly analyzed instead of being stored in the fault bitmap in the automatic test equipment (ATE). Therefore, RA is performed simultaneously with the memory test, and the RA latency is eliminated after the test time. Using the GPU, all possible repair cases are examined in parallel; thus, a high memory repair rate is achieved in a short period of time. Also, GRACE can be applied to practical environments where the structure of memory redundancy is complicated. Experimental results indicate that GRACE is faster than other ATE-based RA methods since it completes the RA almost simultaneously at the end of the test. Additionally, the repair rate of GRACE is always higher than those of the other RA methods.",

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note = "Funding Information: Manuscript received July 20, 2019; revised October 18, 2019; accepted November 12, 2019. Date of publication December 17, 2019; date of current version February 25, 2020. This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea Government (Ministry of Science and ICT) (No. 2019R1A2C3011079). (Corresponding author: Sungho Kang.) The authors are with the Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: incendio9@soc.yonsei.ac.kr; yseehy214@soc.yonsei.ac.kr; shkang@yonsei.ac.kr). Digital Object Identifier 10.1109/TVLSI.2019.2954549 Publisher Copyright: {\textcopyright} 1993-2012 IEEE.",

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GPU-Based Redundancy Analysis Using Concurrent Evaluation

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