GRO-TDC with gate-switch-based delay cell halving resolution limit

Jung Hyun Park, Dong Hoon Jung, Seongook Jung

Research output: Contribution to journalArticle

Abstract

In this paper, we propose a time-to-digital converter (TDC) with first-order noise-shaping. The proposed gated ring oscillator (GRO)-TDC overcomes the limitation associated with GRO's intrinsic resolution by adopting two GROs, whose delay difference is equal to half the delay of a delay cell. The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate-switched configuration to solve the charge redistribution problem. The proposed GRO-TDC is designed using a 65-nm process technology, with an area of 0.015 mm 2 and a supply voltage of 1 V. The sampling rate and the effective resolution of the proposed GRO-TDC are 50 MS/s and 1.22 ps, respectively. Finally, the proposed GRO-TDC consumes a power of 9.08 and 2.41 mW in the calibration and conversion modes, respectively.

Original languageEnglish
JournalInternational Journal of Circuit Theory and Applications
DOIs
Publication statusAccepted/In press - 2017 Jan 1

Fingerprint

Converter
Switch
Switches
Calibration
Sampling
Ring
Cell
Electric potential
Redistribution
Voltage
Charge
First-order
Configuration

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

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abstract = "In this paper, we propose a time-to-digital converter (TDC) with first-order noise-shaping. The proposed gated ring oscillator (GRO)-TDC overcomes the limitation associated with GRO's intrinsic resolution by adopting two GROs, whose delay difference is equal to half the delay of a delay cell. The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate-switched configuration to solve the charge redistribution problem. The proposed GRO-TDC is designed using a 65-nm process technology, with an area of 0.015 mm 2 and a supply voltage of 1 V. The sampling rate and the effective resolution of the proposed GRO-TDC are 50 MS/s and 1.22 ps, respectively. Finally, the proposed GRO-TDC consumes a power of 9.08 and 2.41 mW in the calibration and conversion modes, respectively.",
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GRO-TDC with gate-switch-based delay cell halving resolution limit. / Park, Jung Hyun; Jung, Dong Hoon; Jung, Seongook.

In: International Journal of Circuit Theory and Applications, 01.01.2017.

Research output: Contribution to journalArticle

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