Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs

Young Woo Lee, Hyeonchan Lim, Sungho Kang

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware overhead and test time are proportional to the number of TSVs. In this paper, we propose a new unified test architecture for screening of TSV defects in 3-D-ICs. Depending on the number of assembled TSVs, the proposed grouping-based test architecture can effectively reduce the cumulative test time and hardware overhead without compromising the test quality.

Original languageEnglish
Article number7572121
Pages (from-to)1759-1763
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume36
Issue number10
DOIs
Publication statusPublished - 2017 Oct

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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