After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware overhead and test time are proportional to the number of TSVs. In this paper, we propose a new unified test architecture for screening of TSV defects in 3-D-ICs. Depending on the number of assembled TSVs, the proposed grouping-based test architecture can effectively reduce the cumulative test time and hardware overhead without compromising the test quality.
|Number of pages||5|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - 2017 Oct|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering