Hardware Efficient Built-in Self-Test Architecture for Power and Ground TSVs in 3D IC

Donghyun Han; Youngkwang Lee; Sooryeong Lee; Sungho Kang

doi:10.1109/ISOCC53507.2021.9613959

Hardware Efficient Built-in Self-Test Architecture for Power and Ground TSVs in 3D IC

Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) are widely used as a solution to solve the interconnect and power problems in IC design. However, as the structures of 3D ICs become more complex, testing has emerged as an important challenge. It is difficult to test power and ground TSVs because they are connected to a grid after stacking. In this paper, a built-in self-Test architecture for power and ground TSVs is proposed. This architecture tests for three types of TSV faults that are critical to the operation of TSVs. The proposed test architecture can improve the reliability of 3D stacked IC by providing a suitable test for power and ground TSVs with little hardware overhead.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	101-102
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613959
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by the Samsung Company, Ltd., Hwaseong, Korea.

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613959

Cite this

Han, D., Lee, Y., Lee, S., & Kang, S. (2021). Hardware Efficient Built-in Self-Test Architecture for Power and Ground TSVs in 3D IC. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 101-102). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613959

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abstract = "3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) are widely used as a solution to solve the interconnect and power problems in IC design. However, as the structures of 3D ICs become more complex, testing has emerged as an important challenge. It is difficult to test power and ground TSVs because they are connected to a grid after stacking. In this paper, a built-in self-Test architecture for power and ground TSVs is proposed. This architecture tests for three types of TSV faults that are critical to the operation of TSVs. The proposed test architecture can improve the reliability of 3D stacked IC by providing a suitable test for power and ground TSVs with little hardware overhead.",

author = "Donghyun Han and Youngkwang Lee and Sooryeong Lee and Sungho Kang",

note = "Funding Information: ACKNOWLEDGMENT This work was supported by the Samsung Company, Ltd., Hwaseong, Korea. Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

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language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

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Han, D, Lee, Y, Lee, S & Kang, S 2021, Hardware Efficient Built-in Self-Test Architecture for Power and Ground TSVs in 3D IC. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 101-102, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613959

Hardware Efficient Built-in Self-Test Architecture for Power and Ground TSVs in 3D IC. / Han, Donghyun; Lee, Youngkwang; Lee, Sooryeong et al.

Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 101-102 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - 3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) are widely used as a solution to solve the interconnect and power problems in IC design. However, as the structures of 3D ICs become more complex, testing has emerged as an important challenge. It is difficult to test power and ground TSVs because they are connected to a grid after stacking. In this paper, a built-in self-Test architecture for power and ground TSVs is proposed. This architecture tests for three types of TSV faults that are critical to the operation of TSVs. The proposed test architecture can improve the reliability of 3D stacked IC by providing a suitable test for power and ground TSVs with little hardware overhead.

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Hardware Efficient Built-in Self-Test Architecture for Power and Ground TSVs in 3D IC

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