3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) are widely used as a solution to solve the interconnect and power problems in IC design. However, as the structures of 3D ICs become more complex, testing has emerged as an important challenge. It is difficult to test power and ground TSVs because they are connected to a grid after stacking. In this paper, a built-in self-Test architecture for power and ground TSVs is proposed. This architecture tests for three types of TSV faults that are critical to the operation of TSVs. The proposed test architecture can improve the reliability of 3D stacked IC by providing a suitable test for power and ground TSVs with little hardware overhead.
|Title of host publication||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2021|
|Event||18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of|
Duration: 2021 Oct 6 → 2021 Oct 9
|Name||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Conference||18th International System-on-Chip Design Conference, ISOCC 2021|
|Country/Territory||Korea, Republic of|
|Period||21/10/6 → 21/10/9|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by the Samsung Company, Ltd., Hwaseong, Korea.
© 2021 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Information Systems
- Hardware and Architecture
- Electrical and Electronic Engineering