Hardware implementation of a tessellation accelerator for the openVG standard

Seung Hun Kim, Yunho Oh, Karam Park, Won Woo Ro

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

The OpenVG standard has been introduced as an efficient vector graphics API for embedded systems. There have been several OpenVG implementations that are based on the software rendering of image. However, the software rendering needs more execution time and power consumption than hardware accelerated rendering. For the efficient hardware implementation, we merge eight pipeline stages in the original specification to four pipeline stages. The first hardware acceleration stage is the tessellation part which is one of the pipeline stages that calculates the edge of vector graphics. In this paper, we provide an efficient hardware design for the tessellation stage and claim this would eventually reduce the execution time and hardware complexity.

Original languageEnglish
Pages (from-to)440-446
Number of pages7
Journalieice electronics express
Volume7
Issue number6
DOIs
Publication statusPublished - 2010 Mar 25

Fingerprint

Particle accelerators
hardware
accelerators
Hardware
Pipelines
computer programs
application programming interface
Application programming interfaces (API)
Embedded systems
specifications
Electric power utilization
Specifications

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Kim, Seung Hun ; Oh, Yunho ; Park, Karam ; Ro, Won Woo. / Hardware implementation of a tessellation accelerator for the openVG standard. In: ieice electronics express. 2010 ; Vol. 7, No. 6. pp. 440-446.
@article{844e5c77d7d24548a858881a48c36ffa,
title = "Hardware implementation of a tessellation accelerator for the openVG standard",
abstract = "The OpenVG standard has been introduced as an efficient vector graphics API for embedded systems. There have been several OpenVG implementations that are based on the software rendering of image. However, the software rendering needs more execution time and power consumption than hardware accelerated rendering. For the efficient hardware implementation, we merge eight pipeline stages in the original specification to four pipeline stages. The first hardware acceleration stage is the tessellation part which is one of the pipeline stages that calculates the edge of vector graphics. In this paper, we provide an efficient hardware design for the tessellation stage and claim this would eventually reduce the execution time and hardware complexity.",
author = "Kim, {Seung Hun} and Yunho Oh and Karam Park and Ro, {Won Woo}",
year = "2010",
month = "3",
day = "25",
doi = "10.1587/elex.7.440",
language = "English",
volume = "7",
pages = "440--446",
journal = "IEICE Electronics Express",
issn = "1349-2543",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "6",

}

Hardware implementation of a tessellation accelerator for the openVG standard. / Kim, Seung Hun; Oh, Yunho; Park, Karam; Ro, Won Woo.

In: ieice electronics express, Vol. 7, No. 6, 25.03.2010, p. 440-446.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Hardware implementation of a tessellation accelerator for the openVG standard

AU - Kim, Seung Hun

AU - Oh, Yunho

AU - Park, Karam

AU - Ro, Won Woo

PY - 2010/3/25

Y1 - 2010/3/25

N2 - The OpenVG standard has been introduced as an efficient vector graphics API for embedded systems. There have been several OpenVG implementations that are based on the software rendering of image. However, the software rendering needs more execution time and power consumption than hardware accelerated rendering. For the efficient hardware implementation, we merge eight pipeline stages in the original specification to four pipeline stages. The first hardware acceleration stage is the tessellation part which is one of the pipeline stages that calculates the edge of vector graphics. In this paper, we provide an efficient hardware design for the tessellation stage and claim this would eventually reduce the execution time and hardware complexity.

AB - The OpenVG standard has been introduced as an efficient vector graphics API for embedded systems. There have been several OpenVG implementations that are based on the software rendering of image. However, the software rendering needs more execution time and power consumption than hardware accelerated rendering. For the efficient hardware implementation, we merge eight pipeline stages in the original specification to four pipeline stages. The first hardware acceleration stage is the tessellation part which is one of the pipeline stages that calculates the edge of vector graphics. In this paper, we provide an efficient hardware design for the tessellation stage and claim this would eventually reduce the execution time and hardware complexity.

UR - http://www.scopus.com/inward/record.url?scp=77950283865&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950283865&partnerID=8YFLogxK

U2 - 10.1587/elex.7.440

DO - 10.1587/elex.7.440

M3 - Article

VL - 7

SP - 440

EP - 446

JO - IEICE Electronics Express

JF - IEICE Electronics Express

SN - 1349-2543

IS - 6

ER -