This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefetching techniques at both the hardware and the software levels. Three processors, one for each level of the memory hierarchy, act in concert to mask the memory latency. Our performance evaluation benchmarks include the Data-Intensive Systems Benchmark suite and the DIS Stressmark suite. Our simulation results point to a distinct advantage of the HiDISC system over current prevailing superscalar architectures for both sets of the benchmarks. On the average, a 12% improvement in performance is achieved while 17% of cache misses are eliminated.
|Title of host publication||Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|ISBN (Electronic)||0769519261, 9780769519265|
|Publication status||Published - 2003|
|Event||International Parallel and Distributed Processing Symposium, IPDPS 2003 - Nice, France|
Duration: 2003 Apr 22 → 2003 Apr 26
|Name||Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003|
|Other||International Parallel and Distributed Processing Symposium, IPDPS 2003|
|Period||03/4/22 → 03/4/26|
Bibliographical notePublisher Copyright:
© 2003 IEEE.
All Science Journal Classification (ASJC) codes
- Computational Theory and Mathematics
- Theoretical Computer Science