Hierarchical BSP model supporting processor locality

Hojung Cha, Dongho Lee

Research output: Contribution to conferencePaper

Abstract

This paper presents a parallel computing model, called H-BSP, which adds a hierarchical concept to the BSP (Bulk Synchronous Parallel) computing model. A H-BSP program consists of a number of BSP groups which are dynamically created at run time and executed in a hierarchical fashion. H-BSP allows algorithm designer to develop more efficient algorithm by utilizing processor locality in the program. This paper describes the structure of H-BSP model, complexity analysis and an example of H-BSP algorithm. Also presented is a performance characteristics of H-BSP algorithm based on the simulation analysis. Simulation results show that H-BSP model takes advantages of processor locality and performs well in low bandwidth networks or in a constant-valence architecture such as 2-dimensional mesh. It is also proved that H-BSP model can predict algorithm performance better than BSP model due to its locality preserving nature.

Original languageEnglish
Pages20-27
Number of pages8
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 International Conference on Parallel and Distributed Systems - Seoul, South Korea
Duration: 1997 Dec 101997 Dec 13

Other

OtherProceedings of the 1997 International Conference on Parallel and Distributed Systems
CitySeoul, South Korea
Period97/12/1097/12/13

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Cha, H., & Lee, D. (1997). Hierarchical BSP model supporting processor locality. 20-27. Paper presented at Proceedings of the 1997 International Conference on Parallel and Distributed Systems, Seoul, South Korea, .