For the first time, the DRAM device composed of 6F2 open-bit-line memory cell with 80nm feature size is developed. Adopting 6F 2 scheme instead of customary 8F2 scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F2 accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F 2, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell Vth so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) is introduced. It is the improved scheme of RCAT used in 8F2 scheme. By adopting S-RCAT, Vth can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.