High-MDSI: A high-level signal integrity fault test pattern generation method for interconnects

Chun Sunghoon, Kim Yongjoon, Kang Sungho

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

Original languageEnglish
Title of host publicationProceedings of the 16th Asian Test Symposium, ATS 2007
Pages115-118
Number of pages4
DOIs
Publication statusPublished - 2007
Event16th Asian Test Symposium, ATS 2007 - Beijing, China
Duration: 2007 Oct 82007 Oct 11

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other16th Asian Test Symposium, ATS 2007
CountryChina
CityBeijing
Period07/10/807/10/11

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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