High-MDSI: A high-level signal integrity fault test pattern generation method for interconnects

Chun Sunghoon; Kim Yongjoon; Kang Sungho

doi:10.1109/ATS.2007.4387994

High-MDSI: A high-level signal integrity fault test pattern generation method for interconnects

Chun Sunghoon, Kim Yongjoon, Kang Sungho

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

Original language	English
Title of host publication	Proceedings of the 16th Asian Test Symposium, ATS 2007
Pages	115-118
Number of pages	4
DOIs	https://doi.org/10.1109/ATS.2007.4387994
Publication status	Published - 2007
Event	16th Asian Test Symposium, ATS 2007 - Beijing, China Duration: 2007 Oct 8 → 2007 Oct 11

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Other

Other	16th Asian Test Symposium, ATS 2007
Country/Territory	China
City	Beijing
Period	07/10/8 → 07/10/11

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ATS.2007.4387994

Cite this

@inproceedings{30b287a5c6ab4750a52f5435db0ed1da,

title = "High-MDSI: A high-level signal integrity fault test pattern generation method for interconnects",

abstract = "Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.",

author = "Chun Sunghoon and Kim Yongjoon and Kang Sungho",

year = "2007",

doi = "10.1109/ATS.2007.4387994",

language = "English",

isbn = "0769528902",

series = "Proceedings of the Asian Test Symposium",

pages = "115--118",

booktitle = "Proceedings of the 16th Asian Test Symposium, ATS 2007",

note = "16th Asian Test Symposium, ATS 2007 ; Conference date: 08-10-2007 Through 11-10-2007",

}

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T1 - High-MDSI

T2 - 16th Asian Test Symposium, ATS 2007

AU - Sunghoon, Chun

AU - Yongjoon, Kim

AU - Sungho, Kang

PY - 2007

Y1 - 2007

N2 - Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

AB - Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

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M3 - Conference contribution

AN - SCOPUS:48049124765

SN - 0769528902

SN - 9780769528908

T3 - Proceedings of the Asian Test Symposium

SP - 115

EP - 118

BT - Proceedings of the 16th Asian Test Symposium, ATS 2007

Y2 - 8 October 2007 through 11 October 2007

ER -

High-MDSI: A high-level signal integrity fault test pattern generation method for interconnects

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