High performance hardware accelerator for design-error simulation

Research output: Contribution to journalArticle

Abstract

Error simulation is used to validate designs by providing simulation results, as well as simulation coverage metrics, based on design-error modelling and detection. Hardware acceleration is a viable approach to achieve efficient error simulation for large systems. In this research, the first hardware accelerator for design-error simulation purposes has been developed. The hardware accelerator uses a reconfigurable mesh-type processing element array, with direct mapping strategy, which establishes a basis for good approximation to breadboarding. In addition, a new embedded parallel algorithm is introduced to perform high speed and cost-effective design-error simulation. Using a cost-performance ratio, the performance is compared to a software simulation. Results show that this first hardware accelerator for error simulation is much faster, in terms of computation time, than software simulation and more cost effective.

Original languageEnglish
Pages (from-to)81-87
Number of pages7
JournalIEE Proceedings: Circuits, Devices and Systems
Volume144
Issue number2
DOIs
Publication statusPublished - 1997 Jan 1

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Particle accelerators
Hardware
Costs
Parallel algorithms
Processing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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High performance hardware accelerator for design-error simulation. / Kang, Sungho.

In: IEE Proceedings: Circuits, Devices and Systems, Vol. 144, No. 2, 01.01.1997, p. 81-87.

Research output: Contribution to journalArticle

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