TY - GEN
T1 - High-performance low-power magnetic tunnel junction based non-volatile flip-flop
AU - Na, Taehui
AU - Ryu, Kyungho
AU - Kim, Jisu
AU - Jung, Seong Ook
AU - Kim, Jung Pill
AU - Kang, Seung H.
N1 - Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014
Y1 - 2014
N2 - In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.
AB - In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.
UR - http://www.scopus.com/inward/record.url?scp=84907397945&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2014.6865544
DO - 10.1109/ISCAS.2014.6865544
M3 - Conference contribution
AN - SCOPUS:84907397945
SN - 9781479934324
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1953
EP - 1956
BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Y2 - 1 June 2014 through 5 June 2014
ER -