High-performance low-power magnetic tunnel junction based non-volatile flip-flop

Taehui Na, Kyungho Ryu, Jisu Kim, Seong Ook Jung, Jung Pill Kim, Seung H. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1953-1956
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 2014 Jun 12014 Jun 5

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period14/6/114/6/5

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Na, T., Ryu, K., Kim, J., Jung, S. O., Kim, J. P., & Kang, S. H. (2014). High-performance low-power magnetic tunnel junction based non-volatile flip-flop. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1953-1956). [6865544] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865544