High-performance low-power magnetic tunnel junction based non-volatile flip-flop

Taehui Na; Kyungho Ryu; Jisu Kim; Seong Ook Jung; Jung Pill Kim; Seung H. Kang

doi:10.1109/ISCAS.2014.6865544

High-performance low-power magnetic tunnel junction based non-volatile flip-flop

Taehui Na, Kyungho Ryu, Jisu Kim, Seong Ook Jung, Jung Pill Kim, Seung H. Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1953-1956
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865544
Publication status	Published - 2014 Jan 1
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country	Australia
City	Melbourne, VIC
Period	14/6/1 → 14/6/5

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All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

Na, T., Ryu, K., Kim, J., Jung, S. O., Kim, J. P., & Kang, S. H. (2014). High-performance low-power magnetic tunnel junction based non-volatile flip-flop. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1953-1956). [6865544] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865544

Na, Taehui ; Ryu, Kyungho ; Kim, Jisu ; Jung, Seong Ook ; Kim, Jung Pill ; Kang, Seung H. / High-performance low-power magnetic tunnel junction based non-volatile flip-flop. 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 1953-1956 (Proceedings - IEEE International Symposium on Circuits and Systems).

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abstract = "In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.",

author = "Taehui Na and Kyungho Ryu and Jisu Kim and Jung, {Seong Ook} and Kim, {Jung Pill} and Kang, {Seung H.}",

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Na, T, Ryu, K, Kim, J, Jung, SO, Kim, JP & Kang, SH 2014, High-performance low-power magnetic tunnel junction based non-volatile flip-flop. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865544, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1953-1956, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14/6/1. https://doi.org/10.1109/ISCAS.2014.6865544

High-performance low-power magnetic tunnel junction based non-volatile flip-flop. / Na, Taehui; Ryu, Kyungho; Kim, Jisu; Jung, Seong Ook; Kim, Jung Pill; Kang, Seung H.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 1953-1956 6865544 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

AB - In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

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Na T, Ryu K, Kim J, Jung SO, Kim JP, Kang SH. High-performance low-power magnetic tunnel junction based non-volatile flip-flop. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 1953-1956. 6865544. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2014.6865544

Access to Document

10.1109/ISCAS.2014.6865544