High-performance low-power magnetic tunnel junction based non-volatile flip-flop

Taehui Na, Kyungho Ryu, Jisu Kim, Seongook Jung, Jung Pill Kim, Seung H. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1953-1956
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 2014 Jun 12014 Jun 5

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period14/6/114/6/5

Fingerprint

Tunnel junctions
Flip flop circuits
Networks (circuits)
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Na, T., Ryu, K., Kim, J., Jung, S., Kim, J. P., & Kang, S. H. (2014). High-performance low-power magnetic tunnel junction based non-volatile flip-flop. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1953-1956). [6865544] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865544
Na, Taehui ; Ryu, Kyungho ; Kim, Jisu ; Jung, Seongook ; Kim, Jung Pill ; Kang, Seung H. / High-performance low-power magnetic tunnel junction based non-volatile flip-flop. 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 1953-1956 (Proceedings - IEEE International Symposium on Circuits and Systems).
@inproceedings{ec455190c640487abe2c50ee05c9122b,
title = "High-performance low-power magnetic tunnel junction based non-volatile flip-flop",
abstract = "In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2{\%} smaller layout area than the conventional NVFF.",
author = "Taehui Na and Kyungho Ryu and Jisu Kim and Seongook Jung and Kim, {Jung Pill} and Kang, {Seung H.}",
year = "2014",
month = "1",
day = "1",
doi = "10.1109/ISCAS.2014.6865544",
language = "English",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1953--1956",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
address = "United States",

}

Na, T, Ryu, K, Kim, J, Jung, S, Kim, JP & Kang, SH 2014, High-performance low-power magnetic tunnel junction based non-volatile flip-flop. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865544, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1953-1956, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14/6/1. https://doi.org/10.1109/ISCAS.2014.6865544

High-performance low-power magnetic tunnel junction based non-volatile flip-flop. / Na, Taehui; Ryu, Kyungho; Kim, Jisu; Jung, Seongook; Kim, Jung Pill; Kang, Seung H.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 1953-1956 6865544 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - High-performance low-power magnetic tunnel junction based non-volatile flip-flop

AU - Na, Taehui

AU - Ryu, Kyungho

AU - Kim, Jisu

AU - Jung, Seongook

AU - Kim, Jung Pill

AU - Kang, Seung H.

PY - 2014/1/1

Y1 - 2014/1/1

N2 - In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

AB - In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

UR - http://www.scopus.com/inward/record.url?scp=84907397945&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84907397945&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2014.6865544

DO - 10.1109/ISCAS.2014.6865544

M3 - Conference contribution

SN - 9781479934324

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1953

EP - 1956

BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Na T, Ryu K, Kim J, Jung S, Kim JP, Kang SH. High-performance low-power magnetic tunnel junction based non-volatile flip-flop. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 1953-1956. 6865544. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2014.6865544