In this manuscript, the fabrication of polymer nonvolatile memory cells based on one-transistor-one-transistor (1T1T) device geometries is reported. A spin-coated diketopyrrolopyrrole (DPP)-based polymer semiconductor was used as the active channel layer for both the control transistor (CT) and memory transistor (MT); thermally deposited gold nanoparticles (Au NPs) were inserted between the tunneling and blocking gate dielectrics as a charge-trapping layer of the MT. In the 1T1T memory cell, the source electrode of the CT was connected to the gate electrode of the MT, while the drain electrode of the MT was connected to the gate electrode of the CT. The reading and writing processes of the memory cells operated separately, which yielded a nondestructive read-out capability. The fabricated 1T1T polymer memory cells exhibited excellent device performances with a large memory window of 16.1 V, a high programming-erasing current ratio >103, a long retention of 103 s, a cyclic stability of 500 cycles, and a 2-bit data storage capability. The proposed device architecture provides a feasible method by which to achieve high-performance organic nonvolatile memory.
Bibliographical noteFunding Information:
This work was supported by the Center for Advanced Soft Electronics (CASE) under the Global Frontier Research Program, Korea (NRF-2013M3A6A5073177), the Basic Science Program through the NRF funded by the Ministry of Education (NRF-2015R1D1A1A01058493 and 2017R1A4A1015400), and the R&D Convergence Program of the NST (National Research Council of Science and Technology) of the Republic of Korea (CAP-15-04-KITECH), Korea.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Physical and Theoretical Chemistry
- Surfaces, Coatings and Films