Due to the advance of dynamic random access memory (DRAM) technologies with the steadfast increase of density with aggressively scaled storage capacitors, the supply voltage has been lowered to under 1 V to reduce power consumption. The above progress has been accompanied by the increasingly difficult task of sensing cell data reliably. One of the essential methods to preserve sustainable data retention characteristic is to curtail the sub-threshold leakage current by using a negative voltage bias for the bulk of access transistors. This negative back-bias is generated by a back-bias voltage generator. This paper proposes a novel high-speed back-bias voltage (VBB) generator with a cross-coupled hybrid pumping scheme. The conventional circuit uses one fixed voltage to control the gates of discharge of the p-channel metal oxide semiconductor (PMOS) and transfer n-channel metal oxide semiconductor (NMOS), respectively. However, the proposed circuit adds an auxiliary pump, thereby able to control more aptly with a lower negative voltage when discharging and a higher positive voltage when transferring. As a result, the proposed circuit achieves a faster pump-down speed and higher pumping current at a lower supply voltage compared to conventional circuits. The H-simulation program with integrated circuit emphasis (HSPICE) simulation results with the Taiwan semiconductor manufacturing company (TSMC) 0.18 um process technology indicates that the proposed circuit has about a 20% faster pump-down speed at a supply voltage of voltage common collector (VCC) = 1.2 V and about 3% higher pumping current at VBB from −0.6 V to −1 V with the ability to generate a near 3% higher ratio of |VBB|/VCC at VCC = 0.6 V compared to conventional circuits. Hence, the proposed circuit is extremely suitable and promising for future low-power and high-performance DRAM applications.
Bibliographical noteFunding Information:
Funding: This work was funded by the Ministry of Trade, Industry and Energy under Grant 10067813 and by the Korea Semiconductor Research Consortium Support Program for the Development of the Future Semiconductor Device.
Acknowledgments: This work was supported by Samsung Electronics, and the EDA tools were supported by the IC Design Education Center (IDEC), Korea.
All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
- Signal Processing
- Hardware and Architecture
- Computer Networks and Communications
- Electrical and Electronic Engineering