In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-μm CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%.
|Number of pages||6|
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|Publication status||Published - 2002 Jun|
Bibliographical noteFunding Information:
Manuscript received July 2, 2000; revised May 28, 2002. This work was supported in part by Semiconductor Research Corp. under Grant SRC 98-HJ-641. This paper was recommended by Associate Editor X. Sung.
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering