High-speed CMOS integrated optical receiver with an avalanche photodetector

Jin Sung Youn; Hyo Soon Kang; Myung Jae Lee; Kang Yeob Park; Woo Young Choi

doi:10.1109/LPT.2009.2029869

High-speed CMOS integrated optical receiver with an avalanche photodetector

Jin Sung Youn, Hyo Soon Kang, Myung Jae Lee, Kang Yeob Park, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

27 Citations (Scopus)

Abstract

We present a high-speed monolithically integrated optical receiver fabricated with 0.13- μm standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10 ^-12 at the incident optical power of 5.5 dBm.

Original language	English
Article number	26
Pages (from-to)	1553-1555
Number of pages	3
Journal	IEEE Photonics Technology Letters
Volume	21
Issue number	20
DOIs	https://doi.org/10.1109/LPT.2009.2029869
Publication status	Published - 2009

Bibliographical note

Funding Information:
Manuscript received May 25, 2009; revised July 09, 2009. First published August 25, 2009; current version published October 02, 2009. This work was supported in part by the IT R&D program of MKE/KEIT [2009-F-010-01].

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering

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title = "High-speed CMOS integrated optical receiver with an avalanche photodetector",

abstract = "We present a high-speed monolithically integrated optical receiver fabricated with 0.13- μm standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10 -12 at the incident optical power of 5.5 dBm.",

author = "Youn, {Jin Sung} and Kang, {Hyo Soon} and Lee, {Myung Jae} and Park, {Kang Yeob} and Choi, {Woo Young}",

note = "Funding Information: Manuscript received May 25, 2009; revised July 09, 2009. First published August 25, 2009; current version published October 02, 2009. This work was supported in part by the IT R&D program of MKE/KEIT [2009-F-010-01].",

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AU - Youn, Jin Sung

AU - Kang, Hyo Soon

AU - Lee, Myung Jae

AU - Park, Kang Yeob

AU - Choi, Woo Young

N1 - Funding Information: Manuscript received May 25, 2009; revised July 09, 2009. First published August 25, 2009; current version published October 02, 2009. This work was supported in part by the IT R&D program of MKE/KEIT [2009-F-010-01].

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AB - We present a high-speed monolithically integrated optical receiver fabricated with 0.13- μm standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10 -12 at the incident optical power of 5.5 dBm.

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