High-speed, low-power, and highly reliable frequency multiplier for DLL-based clock generator

Kyungho Ryu, Jiwan Jung, Dong Hoon Jung, Jin Hyuk Kim, Seong Ook Jung

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-μm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 μW/MHz.

Original languageEnglish
Article number7202907
Pages (from-to)1484-1492
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number4
DOIs
Publication statusPublished - 2016 Apr 1

Fingerprint

Frequency multiplying circuits
Clocks
Logic design
Pulse generators
Jitter
Numerical analysis
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{f37f5c8f85b944eda0794fa72a5ed298,
title = "High-speed, low-power, and highly reliable frequency multiplier for DLL-based clock generator",
abstract = "A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-μm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 μW/MHz.",
author = "Kyungho Ryu and Jiwan Jung and Jung, {Dong Hoon} and Kim, {Jin Hyuk} and Jung, {Seong Ook}",
year = "2016",
month = "4",
day = "1",
doi = "10.1109/TVLSI.2015.2453366",
language = "English",
volume = "24",
pages = "1484--1492",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

High-speed, low-power, and highly reliable frequency multiplier for DLL-based clock generator. / Ryu, Kyungho; Jung, Jiwan; Jung, Dong Hoon; Kim, Jin Hyuk; Jung, Seong Ook.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 4, 7202907, 01.04.2016, p. 1484-1492.

Research output: Contribution to journalArticle

TY - JOUR

T1 - High-speed, low-power, and highly reliable frequency multiplier for DLL-based clock generator

AU - Ryu, Kyungho

AU - Jung, Jiwan

AU - Jung, Dong Hoon

AU - Kim, Jin Hyuk

AU - Jung, Seong Ook

PY - 2016/4/1

Y1 - 2016/4/1

N2 - A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-μm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 μW/MHz.

AB - A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-μm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 μW/MHz.

UR - http://www.scopus.com/inward/record.url?scp=84939421057&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84939421057&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2015.2453366

DO - 10.1109/TVLSI.2015.2453366

M3 - Article

VL - 24

SP - 1484

EP - 1492

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 4

M1 - 7202907

ER -