High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers

D. Lee, Gunhee Han

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

A high-speed, low-power correlated double sampling counter for column parallel CMOS imagers is proposed. Unlike a conventional up/down counter, the proposed counter performs correlated double sampling using a two's complement arithmetic. The proposed counter can be implemented using only 16 transistors per bit. Simulation results show 32 reduction of power consumption and 2.4 times improvement of maximum speed over a conventional up/down counter.

Original languageEnglish
Pages (from-to)1362-1364
Number of pages3
JournalElectronics Letters
Volume43
Issue number24
DOIs
Publication statusPublished - 2007 Nov 30

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Image sensors
Sampling
Transistors
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "A high-speed, low-power correlated double sampling counter for column parallel CMOS imagers is proposed. Unlike a conventional up/down counter, the proposed counter performs correlated double sampling using a two's complement arithmetic. The proposed counter can be implemented using only 16 transistors per bit. Simulation results show 32 reduction of power consumption and 2.4 times improvement of maximum speed over a conventional up/down counter.",
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High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers. / Lee, D.; Han, Gunhee.

In: Electronics Letters, Vol. 43, No. 24, 30.11.2007, p. 1362-1364.

Research output: Contribution to journalArticle

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