High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers

D. Lee, G. Han

Research output: Contribution to journalArticle

22 Citations (Scopus)

Abstract

A high-speed, low-power correlated double sampling counter for column parallel CMOS imagers is proposed. Unlike a conventional up/down counter, the proposed counter performs correlated double sampling using a two's complement arithmetic. The proposed counter can be implemented using only 16 transistors per bit. Simulation results show 32 reduction of power consumption and 2.4 times improvement of maximum speed over a conventional up/down counter.

Original languageEnglish
Pages (from-to)1362-1364
Number of pages3
JournalElectronics Letters
Volume43
Issue number24
DOIs
Publication statusPublished - 2007 Nov 30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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