A high-speed, low-power correlated double sampling counter for column parallel CMOS imagers is proposed. Unlike a conventional up/down counter, the proposed counter performs correlated double sampling using a two's complement arithmetic. The proposed counter can be implemented using only 16 transistors per bit. Simulation results show 32 reduction of power consumption and 2.4 times improvement of maximum speed over a conventional up/down counter.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering