High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths

Sang Uhn Cha; Hongil Yoon

doi:10.1109/iscas.2007.377984

High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths

Sang Uhn Cha, Hongil Yoon

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Citations (Scopus)

Abstract

Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.

Original language	English
Article number	4253316
Pages (from-to)	3026-3029
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/iscas.2007.377984
Publication status	Published - 2007
Event	2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 2007 May 27 → 2007 May 30

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/iscas.2007.377984

Cite this

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title = "High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths",

abstract = "Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.",

author = "Cha, {Sang Uhn} and Hongil Yoon",

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doi = "10.1109/iscas.2007.377984",

language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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T1 - High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths

AU - Cha, Sang Uhn

AU - Yoon, Hongil

PY - 2007

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N2 - Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.

AB - Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

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T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

Y2 - 27 May 2007 through 30 May 2007

ER -

High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths

Abstract

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