High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths

Sang Uhn Cha, Hongil Yoon

Research output: Contribution to journalConference article

7 Citations (Scopus)

Abstract

Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.

Original languageEnglish
Article number4253316
Pages (from-to)3026-3029
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2007 Sep 27

Fingerprint

Dynamic random access storage
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{0b51b5b4dc72458baeb1ceb7cd4b8677,
title = "High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths",
abstract = "Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7{\%} at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.",
author = "Cha, {Sang Uhn} and Hongil Yoon",
year = "2007",
month = "9",
day = "27",
language = "English",
pages = "3026--3029",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. / Cha, Sang Uhn; Yoon, Hongil.

In: Proceedings - IEEE International Symposium on Circuits and Systems, 27.09.2007, p. 3026-3029.

Research output: Contribution to journalConference article

TY - JOUR

T1 - High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths

AU - Cha, Sang Uhn

AU - Yoon, Hongil

PY - 2007/9/27

Y1 - 2007/9/27

N2 - Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.

AB - Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.

UR - http://www.scopus.com/inward/record.url?scp=34548828557&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548828557&partnerID=8YFLogxK

M3 - Conference article

SP - 3026

EP - 3029

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

M1 - 4253316

ER -