Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability

Sehee Lim, Byungkyu Song, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

In physically unclonable functions (PUFs), generating random cryptographs is required to secure private information. Various memory-based PUFs (MemPUFs), where cryptographs are generated independently from each PUF cell to increase the unpredictability of the cryptographs, have been proposed. Among them, the spin-transfer torque magnetic random-access memory MemPUF generates constant responses under temperature and voltage variations by exploiting a magnetic tunnel junction (MTJ) as the variation source. However, its response stability is diminished by the different characteristics of the two access transistors used in a PUF cell. To solve this problem, a novel PUF array that employs a diode-connected transistor and a shared access transistor, is proposed. In addition, a two-step postprocessing is adopted: 1) a write-back technique that amplifies the initial mismatch of MTJ resistances, and 2) a cell-classification technique that detects unstable PUF cells and discards their responses. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm technology show that the proposed PUF system achieves the highest independence (autocorrelation factor of 0.0306) and the lowest maximum bit error rate (BER) under temperature and supply-voltage variations (<0.01% and 0.04% in the ranges of -25 to 75 °C and 0.8-1.2 V, respectively) compared with conventional PUF systems that exploit independent variation sources.

Original languageEnglish
Article number9020171
Pages (from-to)2798-2807
Number of pages10
JournalIEEE Transactions on Information Forensics and Security
Volume15
DOIs
Publication statusPublished - 2020

Bibliographical note

Funding Information:
Manuscript received October 2, 2019; revised January 6, 2020 and February 13, 2020; accepted February 21, 2020. Date of publication March 2, 2020; date of current version March 24, 2020. This work was supported in part by the Future Semiconductor New Device Source Technology Development Project of IITP, Polarization-Switching Dielectric Based Memory Transistor and its Nonvolatile Logic Architecture under Grant 1711097930. The associate editor coordinating the review of this manuscript and approving it for publication was Prof. Georg Sigl. (Corresponding author: Seong-Ook Jung.) The authors are with the School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: sjung@yonsei.ac.kr). Digital Object Identifier 10.1109/TIFS.2020.2976623

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Computer Networks and Communications

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