Highly manufacturable and high performance SDR/DDR 4Gb DRAM

K. N. Kim, H. S. Jeong, W. S. Yang, Y. S. Hwang, C. H. Cho, M. M. Jeong, S. Park, S. J. Ahn, Y. S. Chun, S. H. Shin, J. S. Park, S. H. Song, J. Y. Lee, S. M. Jang, C. H. Lee, J. H. Jeong, M. H. Cho, H. I. Yoon, J. S. Jeon

Research output: Contribution to conferencePaperpeer-review

7 Citations (Scopus)

Abstract

A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

Original languageEnglish
Pages7-8
Number of pages2
Publication statusPublished - 2001
Event2001 VLSI Technology Symposium - Kyoto, Japan
Duration: 2001 Jun 122001 Jun 14

Other

Other2001 VLSI Technology Symposium
Country/TerritoryJapan
CityKyoto
Period01/6/1201/6/14

Bibliographical note

Funding Information:
This work was supported by the Ministero dell'Università e della Ricerca Scientifica e Tecnologica and by the Italian Ministry of Health, CF Project, law 548/93.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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