Highly manufacturable and high performance SDR/DDR 4Gb DRAM

K. N. Kim, H. S. Jeong, W. S. Yang, Y. S. Hwang, C. H. Cho, M. M. Jeong, S. Park, S. J. Ahn, Y. S. Chun, S. H. Shin, J. S. Park, S. H. Song, J. Y. Lee, S. M. Jang, C. H. Lee, J. H. Jeong, M. H. Cho, H. I. Yoon, J. S. Jeon

Research output: Contribution to conferencePaper

7 Citations (Scopus)


A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

Original languageEnglish
Number of pages2
Publication statusPublished - 2001 Jan 1
Event2001 VLSI Technology Symposium - Kyoto, Japan
Duration: 2001 Jun 122001 Jun 14


Other2001 VLSI Technology Symposium

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Kim, K. N., Jeong, H. S., Yang, W. S., Hwang, Y. S., Cho, C. H., Jeong, M. M., Park, S., Ahn, S. J., Chun, Y. S., Shin, S. H., Park, J. S., Song, S. H., Lee, J. Y., Jang, S. M., Lee, C. H., Jeong, J. H., Cho, M. H., Yoon, H. I., & Jeon, J. S. (2001). Highly manufacturable and high performance SDR/DDR 4Gb DRAM. 7-8. Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.