A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.
|Number of pages||2|
|Publication status||Published - 2001|
|Event||2001 VLSI Technology Symposium - Kyoto, Japan|
Duration: 2001 Jun 12 → 2001 Jun 14
|Other||2001 VLSI Technology Symposium|
|Period||01/6/12 → 01/6/14|
Bibliographical noteFunding Information:
This work was supported by the Ministero dell'Università e della Ricerca Scientifica e Tecnologica and by the Italian Ministry of Health, CF Project, law 548/93.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering