Highly manufacturable and high performance SDR/DDR 4Gb DRAM

K. N. Kim, H. S. Jeong, W. S. Yang, Y. S. Hwang, C. H. Cho, M. M. Jeong, S. Park, S. J. Ahn, Y. S. Chun, S. H. Shin, J. S. Park, S. H. Song, J. Y. Lee, S. M. Jang, C. H. Lee, J. H. Jeong, Mann-Ho Cho, Hong Il Yoon, J. S. Jeon

Research output: Contribution to conferencePaper

7 Citations (Scopus)

Abstract

A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

Original languageEnglish
Pages7-8
Number of pages2
Publication statusPublished - 2001 Jan 1
Event2001 VLSI Technology Symposium - Kyoto, Japan
Duration: 2001 Jun 122001 Jun 14

Other

Other2001 VLSI Technology Symposium
CountryJapan
CityKyoto
Period01/6/1201/6/14

Fingerprint

Dynamic random access storage
Capacitors
Management information systems
Lithography
Chemical vapor deposition
Transistors
Data storage equipment
Temperature

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kim, K. N., Jeong, H. S., Yang, W. S., Hwang, Y. S., Cho, C. H., Jeong, M. M., ... Jeon, J. S. (2001). Highly manufacturable and high performance SDR/DDR 4Gb DRAM. 7-8. Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.
Kim, K. N. ; Jeong, H. S. ; Yang, W. S. ; Hwang, Y. S. ; Cho, C. H. ; Jeong, M. M. ; Park, S. ; Ahn, S. J. ; Chun, Y. S. ; Shin, S. H. ; Park, J. S. ; Song, S. H. ; Lee, J. Y. ; Jang, S. M. ; Lee, C. H. ; Jeong, J. H. ; Cho, Mann-Ho ; Yoon, Hong Il ; Jeon, J. S. / Highly manufacturable and high performance SDR/DDR 4Gb DRAM. Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.2 p.
@conference{59ee61ece78d4e43a04ef9f98a5ba92a,
title = "Highly manufacturable and high performance SDR/DDR 4Gb DRAM",
abstract = "A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.",
author = "Kim, {K. N.} and Jeong, {H. S.} and Yang, {W. S.} and Hwang, {Y. S.} and Cho, {C. H.} and Jeong, {M. M.} and S. Park and Ahn, {S. J.} and Chun, {Y. S.} and Shin, {S. H.} and Park, {J. S.} and Song, {S. H.} and Lee, {J. Y.} and Jang, {S. M.} and Lee, {C. H.} and Jeong, {J. H.} and Mann-Ho Cho and Yoon, {Hong Il} and Jeon, {J. S.}",
year = "2001",
month = "1",
day = "1",
language = "English",
pages = "7--8",
note = "2001 VLSI Technology Symposium ; Conference date: 12-06-2001 Through 14-06-2001",

}

Kim, KN, Jeong, HS, Yang, WS, Hwang, YS, Cho, CH, Jeong, MM, Park, S, Ahn, SJ, Chun, YS, Shin, SH, Park, JS, Song, SH, Lee, JY, Jang, SM, Lee, CH, Jeong, JH, Cho, M-H, Yoon, HI & Jeon, JS 2001, 'Highly manufacturable and high performance SDR/DDR 4Gb DRAM' Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan, 01/6/12 - 01/6/14, pp. 7-8.

Highly manufacturable and high performance SDR/DDR 4Gb DRAM. / Kim, K. N.; Jeong, H. S.; Yang, W. S.; Hwang, Y. S.; Cho, C. H.; Jeong, M. M.; Park, S.; Ahn, S. J.; Chun, Y. S.; Shin, S. H.; Park, J. S.; Song, S. H.; Lee, J. Y.; Jang, S. M.; Lee, C. H.; Jeong, J. H.; Cho, Mann-Ho; Yoon, Hong Il; Jeon, J. S.

2001. 7-8 Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.

Research output: Contribution to conferencePaper

TY - CONF

T1 - Highly manufacturable and high performance SDR/DDR 4Gb DRAM

AU - Kim, K. N.

AU - Jeong, H. S.

AU - Yang, W. S.

AU - Hwang, Y. S.

AU - Cho, C. H.

AU - Jeong, M. M.

AU - Park, S.

AU - Ahn, S. J.

AU - Chun, Y. S.

AU - Shin, S. H.

AU - Park, J. S.

AU - Song, S. H.

AU - Lee, J. Y.

AU - Jang, S. M.

AU - Lee, C. H.

AU - Jeong, J. H.

AU - Cho, Mann-Ho

AU - Yoon, Hong Il

AU - Jeon, J. S.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

AB - A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

UR - http://www.scopus.com/inward/record.url?scp=0034793533&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034793533&partnerID=8YFLogxK

M3 - Paper

SP - 7

EP - 8

ER -

Kim KN, Jeong HS, Yang WS, Hwang YS, Cho CH, Jeong MM et al. Highly manufacturable and high performance SDR/DDR 4Gb DRAM. 2001. Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.