Highly optimized intra prediction architecture for high resolution application

Jinha Choi, Jeyun Yu, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a new intra prediction architecture for high resolution applications. The standard intra prediction has a data dependency for the pipelined processing. To enable the pipelined intra prediction architecture, processing order changing methods and additional processing schedulers are proposed. However, previous methods are not considered for the parallel processing which is a key issue of high resolution applications, such as High Definition videos or Ultra High Definition videos. The proposed intra prediction architecture has a new scheduler and two difference calculation processing units for the high performance parallel processing in intra 44 luminance prediction and intra 8x8 luminance prediction. The proposed architecture reduces processing time by about 43.40% compared with the standard and by about 20.10% compared with previous architecture.

Original languageEnglish
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages390-393
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: 2010 Dec 62010 Dec 9

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period10/12/610/12/9

Fingerprint

Processing
Luminance

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Choi, J., Yu, J., & Kim, J. (2010). Highly optimized intra prediction architecture for high resolution application. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 (pp. 390-393). [5775074] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5775074
Choi, Jinha ; Yu, Jeyun ; Kim, Jaeseok. / Highly optimized intra prediction architecture for high resolution application. Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. pp. 390-393 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).
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title = "Highly optimized intra prediction architecture for high resolution application",
abstract = "This paper proposes a new intra prediction architecture for high resolution applications. The standard intra prediction has a data dependency for the pipelined processing. To enable the pipelined intra prediction architecture, processing order changing methods and additional processing schedulers are proposed. However, previous methods are not considered for the parallel processing which is a key issue of high resolution applications, such as High Definition videos or Ultra High Definition videos. The proposed intra prediction architecture has a new scheduler and two difference calculation processing units for the high performance parallel processing in intra 44 luminance prediction and intra 8x8 luminance prediction. The proposed architecture reduces processing time by about 43.40{\%} compared with the standard and by about 20.10{\%} compared with previous architecture.",
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Choi, J, Yu, J & Kim, J 2010, Highly optimized intra prediction architecture for high resolution application. in Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010., 5775074, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 390-393, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, Malaysia, 10/12/6. https://doi.org/10.1109/APCCAS.2010.5775074

Highly optimized intra prediction architecture for high resolution application. / Choi, Jinha; Yu, Jeyun; Kim, Jaeseok.

Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 390-393 5775074 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Choi J, Yu J, Kim J. Highly optimized intra prediction architecture for high resolution application. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 390-393. 5775074. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5775074