A three-dimensional (3-D) integration technology involving the use of a through-silicon-via (TSV) offers advantages such as low power consumption, small form factor, and large bandwidth. However, owing to the incompleteness of the 3-D manufacturing process, TSVs may exhibit some inherent defects; hence, switching and shifting repairing methods have been proposed. These methods repair the TSV faults by rerouting the signals of the faulty TSVs to the other signal TSVs or redundant TSVs using a simple repair algorithm. However, if one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the FTSV increases, i.e., the TSV defects tend to be clustered. Therefore, recently proposed repair solutions, such as ring/router-based repair architectures, have focused on clustered TSV faults. However, the implementation of these existing repair solutions for clustered faults involves an extremely high hardware overhead. This study proposes a TSV redundancy architecture to repair clustered TSV faults with a high repair rate and low hardware overhead. The proposed architecture divides the TSVs into several groups and connects the TSVs of each group using a 2:1 multiplexer chain. Simulation results show that the proposed architecture exhibits a repair rate of 98.52% for uniformly distributed faults and 69.86% for highly clustered faults. These repair rates are higher than those of other TSV redundancy architectures and the difference in the repair rate becomes even greater if the faults are more clustered. Moreover, the approach yields a 58.55% reduced area as compared to that of the router-based redundancy architecture, which also targets the repair of clustered faults.
Bibliographical noteFunding Information:
Manuscript received September 15, 2017; revised January 8, 2018 and May 10, 2018; accepted August 5, 2018. Date of publication August 22, 2018; date of current version February 26, 2019. This work was supported by Samsung Electronics Company, Ltd., Hwasung, South Korea. Associate Editor: W.-T. K. Chien. (Corresponding author: Sungho Kang.) The authors are with the Computer System and Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail:,email@example.com; firstname.lastname@example.org. ac.kr; email@example.com).
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering