Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology

Sung Woong Chung, Sang Don Lee, Se Aug Jang, Min Soo Yoo, Kwang Ok Kim, Chai O. Chung, Sung Yoon Cho, Heung Jae Cho, Lae Hee Lee, Sun Hwan Hwang, Jin Soo Kim, Bong Hoon Lee, Hyo Geun Yoon, Hyung Soon Park, Seung Joo Baek, Yun Seok Cho, Noh Jung Kwak, Hyun Chul Sohn, Seung Chan Moon, Kyung Dong YooJae Goan Jeong, Jin Woong Kim, Sung Joo Hong, Sung Wook Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages32-33
Number of pages2
ISBN (Print)1424400058, 9781424400058
Publication statusPublished - 2006 Jan 1
Event2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States
Duration: 2006 Jun 132006 Jun 15

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2006 Symposium on VLSI Technology, VLSIT
CountryUnited States
CityHonolulu, HI
Period06/6/1306/6/15

Fingerprint

Dynamic random access storage
Transistors
Threshold voltage
FinFET

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chung, S. W., Lee, S. D., Jang, S. A., Yoo, M. S., Kim, K. O., Chung, C. O., ... Park, S. W. (2006). Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. In 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers (pp. 32-33). [1705202] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc..
Chung, Sung Woong ; Lee, Sang Don ; Jang, Se Aug ; Yoo, Min Soo ; Kim, Kwang Ok ; Chung, Chai O. ; Cho, Sung Yoon ; Cho, Heung Jae ; Lee, Lae Hee ; Hwang, Sun Hwan ; Kim, Jin Soo ; Lee, Bong Hoon ; Yoon, Hyo Geun ; Park, Hyung Soon ; Baek, Seung Joo ; Cho, Yun Seok ; Kwak, Noh Jung ; Sohn, Hyun Chul ; Moon, Seung Chan ; Yoo, Kyung Dong ; Jeong, Jae Goan ; Kim, Jin Woong ; Hong, Sung Joo ; Park, Sung Wook. / Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2006. pp. 32-33 (Digest of Technical Papers - Symposium on VLSI Technology).
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abstract = "Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.",
author = "Chung, {Sung Woong} and Lee, {Sang Don} and Jang, {Se Aug} and Yoo, {Min Soo} and Kim, {Kwang Ok} and Chung, {Chai O.} and Cho, {Sung Yoon} and Cho, {Heung Jae} and Lee, {Lae Hee} and Hwang, {Sun Hwan} and Kim, {Jin Soo} and Lee, {Bong Hoon} and Yoon, {Hyo Geun} and Park, {Hyung Soon} and Baek, {Seung Joo} and Cho, {Yun Seok} and Kwak, {Noh Jung} and Sohn, {Hyun Chul} and Moon, {Seung Chan} and Yoo, {Kyung Dong} and Jeong, {Jae Goan} and Kim, {Jin Woong} and Hong, {Sung Joo} and Park, {Sung Wook}",
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Chung, SW, Lee, SD, Jang, SA, Yoo, MS, Kim, KO, Chung, CO, Cho, SY, Cho, HJ, Lee, LH, Hwang, SH, Kim, JS, Lee, BH, Yoon, HG, Park, HS, Baek, SJ, Cho, YS, Kwak, NJ, Sohn, HC, Moon, SC, Yoo, KD, Jeong, JG, Kim, JW, Hong, SJ & Park, SW 2006, Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. in 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers., 1705202, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., pp. 32-33, 2006 Symposium on VLSI Technology, VLSIT, Honolulu, HI, United States, 06/6/13.

Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. / Chung, Sung Woong; Lee, Sang Don; Jang, Se Aug; Yoo, Min Soo; Kim, Kwang Ok; Chung, Chai O.; Cho, Sung Yoon; Cho, Heung Jae; Lee, Lae Hee; Hwang, Sun Hwan; Kim, Jin Soo; Lee, Bong Hoon; Yoon, Hyo Geun; Park, Hyung Soon; Baek, Seung Joo; Cho, Yun Seok; Kwak, Noh Jung; Sohn, Hyun Chul; Moon, Seung Chan; Yoo, Kyung Dong; Jeong, Jae Goan; Kim, Jin Woong; Hong, Sung Joo; Park, Sung Wook.

2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2006. p. 32-33 1705202 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Hwang, Sun Hwan

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AB - Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.

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M3 - Conference contribution

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T3 - Digest of Technical Papers - Symposium on VLSI Technology

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BT - 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

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Chung SW, Lee SD, Jang SA, Yoo MS, Kim KO, Chung CO et al. Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. In 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2006. p. 32-33. 1705202. (Digest of Technical Papers - Symposium on VLSI Technology).