Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology

Sung Woong Chung; Sang Don Lee; Se Aug Jang; Min Soo Yoo; Kwang Ok Kim; Chai O. Chung; Sung Yoon Cho; Heung Jae Cho; Lae Hee Lee; Sun Hwan Hwang; Jin Soo Kim; Bong Hoon Lee; Hyo Geun Yoon; Hyung Soon Park; Seung Joo Baek; Yun Seok Cho; Noh Jung Kwak; Hyun Chul Sohn; Seung Chan Moon; Kyung Dong Yoo; Jae Goan Jeong; Jin Woong Kim; Sung Joo Hong; Sung Wook Park

doi:10.1109/vlsit.2006.1705202

Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology

Sung Woong Chung, Sang Don Lee, Se Aug Jang, Min Soo Yoo, Kwang Ok Kim, Chai O. Chung, Sung Yoon Cho, Heung Jae Cho, Lae Hee Lee, Sun Hwan Hwang, Jin Soo Kim, Bong Hoon Lee, Hyo Geun Yoon, Hyung Soon Park, Seung Joo Baek, Yun Seok Cho, Noh Jung Kwak, Hyun Chul Sohn, Seung Chan Moon, Kyung Dong YooJae Goan Jeong, Jin Woong Kim, Sung Joo Hong, Sung Wook Park

Department of Materials Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

29 Citations (Scopus)

Abstract

Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.

Original language	English
Title of host publication	2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	32-33
Number of pages	2
ISBN (Print)	1424400058, 9781424400058
DOIs	https://doi.org/10.1109/vlsit.2006.1705202
Publication status	Published - 2006
Event	2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States Duration: 2006 Jun 13 → 2006 Jun 15

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2006 Symposium on VLSI Technology, VLSIT
Country	United States
City	Honolulu, HI
Period	06/6/13 → 06/6/15

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/vlsit.2006.1705202

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Chung, S. W., Lee, S. D., Jang, S. A., Yoo, M. S., Kim, K. O., Chung, C. O., Cho, S. Y., Cho, H. J., Lee, L. H., Hwang, S. H., Kim, J. S., Lee, B. H., Yoon, H. G., Park, H. S., Baek, S. J., Cho, Y. S., Kwak, N. J., Sohn, H. C., Moon, S. C., ... Park, S. W. (2006). Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. In 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers (pp. 32-33). [1705202] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/vlsit.2006.1705202

Chung, Sung Woong ; Lee, Sang Don ; Jang, Se Aug ; Yoo, Min Soo ; Kim, Kwang Ok ; Chung, Chai O. ; Cho, Sung Yoon ; Cho, Heung Jae ; Lee, Lae Hee ; Hwang, Sun Hwan ; Kim, Jin Soo ; Lee, Bong Hoon ; Yoon, Hyo Geun ; Park, Hyung Soon ; Baek, Seung Joo ; Cho, Yun Seok ; Kwak, Noh Jung ; Sohn, Hyun Chul ; Moon, Seung Chan ; Yoo, Kyung Dong ; Jeong, Jae Goan ; Kim, Jin Woong ; Hong, Sung Joo ; Park, Sung Wook. / Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2006. pp. 32-33 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{7cae7950801f45fab7d8eb4450ca8f39,

title = "Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology",

abstract = "Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.",

author = "Chung, {Sung Woong} and Lee, {Sang Don} and Jang, {Se Aug} and Yoo, {Min Soo} and Kim, {Kwang Ok} and Chung, {Chai O.} and Cho, {Sung Yoon} and Cho, {Heung Jae} and Lee, {Lae Hee} and Hwang, {Sun Hwan} and Kim, {Jin Soo} and Lee, {Bong Hoon} and Yoon, {Hyo Geun} and Park, {Hyung Soon} and Baek, {Seung Joo} and Cho, {Yun Seok} and Kwak, {Noh Jung} and Sohn, {Hyun Chul} and Moon, {Seung Chan} and Yoo, {Kyung Dong} and Jeong, {Jae Goan} and Kim, {Jin Woong} and Hong, {Sung Joo} and Park, {Sung Wook}",

year = "2006",

doi = "10.1109/vlsit.2006.1705202",

language = "English",

isbn = "1424400058",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "32--33",

booktitle = "2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers",

address = "United States",

note = "2006 Symposium on VLSI Technology, VLSIT ; Conference date: 13-06-2006 Through 15-06-2006",

}

Chung, SW, Lee, SD, Jang, SA, Yoo, MS, Kim, KO, Chung, CO, Cho, SY, Cho, HJ, Lee, LH, Hwang, SH, Kim, JS, Lee, BH, Yoon, HG, Park, HS, Baek, SJ, Cho, YS, Kwak, NJ, Sohn, HC, Moon, SC, Yoo, KD, Jeong, JG, Kim, JW, Hong, SJ & Park, SW 2006, Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. in 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers., 1705202, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., pp. 32-33, 2006 Symposium on VLSI Technology, VLSIT, Honolulu, HI, United States, 06/6/13. https://doi.org/10.1109/vlsit.2006.1705202

Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. / Chung, Sung Woong; Lee, Sang Don; Jang, Se Aug; Yoo, Min Soo; Kim, Kwang Ok; Chung, Chai O.; Cho, Sung Yoon; Cho, Heung Jae; Lee, Lae Hee; Hwang, Sun Hwan; Kim, Jin Soo; Lee, Bong Hoon; Yoon, Hyo Geun; Park, Hyung Soon; Baek, Seung Joo; Cho, Yun Seok; Kwak, Noh Jung; Sohn, Hyun Chul; Moon, Seung Chan; Yoo, Kyung Dong; Jeong, Jae Goan; Kim, Jin Woong; Hong, Sung Joo; Park, Sung Wook.

2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2006. p. 32-33 1705202 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology

AU - Chung, Sung Woong

AU - Lee, Sang Don

AU - Jang, Se Aug

AU - Yoo, Min Soo

AU - Kim, Kwang Ok

AU - Chung, Chai O.

AU - Cho, Sung Yoon

AU - Cho, Heung Jae

AU - Lee, Lae Hee

AU - Hwang, Sun Hwan

AU - Kim, Jin Soo

AU - Lee, Bong Hoon

AU - Yoon, Hyo Geun

AU - Park, Hyung Soon

AU - Baek, Seung Joo

AU - Cho, Yun Seok

AU - Kwak, Noh Jung

AU - Sohn, Hyun Chul

AU - Moon, Seung Chan

AU - Yoo, Kyung Dong

AU - Jeong, Jae Goan

AU - Kim, Jin Woong

AU - Hong, Sung Joo

AU - Park, Sung Wook

PY - 2006

Y1 - 2006

N2 - Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.

AB - Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.

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U2 - 10.1109/vlsit.2006.1705202

DO - 10.1109/vlsit.2006.1705202

M3 - Conference contribution

AN - SCOPUS:41149147144

SN - 1424400058

SN - 9781424400058

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 32

EP - 33

BT - 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 Symposium on VLSI Technology, VLSIT

Y2 - 13 June 2006 through 15 June 2006

ER -

Chung SW, Lee SD, Jang SA, Yoo MS, Kim KO, Chung CO et al. Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. In 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2006. p. 32-33. 1705202. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/vlsit.2006.1705202

Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology

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