Abstract
Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.
| Original language | English |
|---|---|
| Title of host publication | 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 32-33 |
| Number of pages | 2 |
| ISBN (Print) | 1424400058, 9781424400058 |
| Publication status | Published - 2006 Jan 1 |
| Event | 2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States Duration: 2006 Jun 13 → 2006 Jun 15 |
Publication series
| Name | Digest of Technical Papers - Symposium on VLSI Technology |
|---|---|
| ISSN (Print) | 0743-1562 |
Other
| Other | 2006 Symposium on VLSI Technology, VLSIT |
|---|---|
| Country | United States |
| City | Honolulu, HI |
| Period | 06/6/13 → 06/6/15 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
Chung, S. W., Lee, S. D., Jang, S. A., Yoo, M. S., Kim, K. O., Chung, C. O., Cho, S. Y., Cho, H. J., Lee, L. H., Hwang, S. H., Kim, J. S., Lee, B. H., Yoon, H. G., Park, H. S., Baek, S. J., Cho, Y. S., Kwak, N. J., Sohn, H. C., Moon, S. C., ... Park, S. W. (2006). Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. In 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers (pp. 32-33). [1705202] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc..