Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology

Sung Woong Chung, Sang Don Lee, Se Aug Jang, Min Soo Yoo, Kwang Ok Kim, Chai O. Chung, Sung Yoon Cho, Heung Jae Cho, Lae Hee Lee, Sun Hwan Hwang, Jin Soo Kim, Bong Hoon Lee, Hyo Geun Yoon, Hyung Soon Park, Seung Joo Baek, Yun Seok Cho, Noh Jung Kwak, Hyun Chul Sohn, Seung Chan Moon, Kyung Dong YooJae Goan Jeong, Jin Woong Kim, Sung Joo Hong, Sung Wook Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)


Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Print)1424400058, 9781424400058
Publication statusPublished - 2006
Event2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States
Duration: 2006 Jun 132006 Jun 15

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562


Other2006 Symposium on VLSI Technology, VLSIT
Country/TerritoryUnited States
CityHonolulu, HI

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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