Abstract
Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.
| Original language | English |
|---|---|
| Title of host publication | 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 32-33 |
| Number of pages | 2 |
| ISBN (Print) | 1424400058, 9781424400058 |
| Publication status | Published - 2006 Jan 1 |
| Event | 2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States Duration: 2006 Jun 13 → 2006 Jun 15 |
Publication series
| Name | Digest of Technical Papers - Symposium on VLSI Technology |
|---|---|
| ISSN (Print) | 0743-1562 |
Other
| Other | 2006 Symposium on VLSI Technology, VLSIT |
|---|---|
| Country | United States |
| City | Honolulu, HI |
| Period | 06/6/13 → 06/6/15 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
}
Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology. / Chung, Sung Woong; Lee, Sang Don; Jang, Se Aug; Yoo, Min Soo; Kim, Kwang Ok; Chung, Chai O.; Cho, Sung Yoon; Cho, Heung Jae; Lee, Lae Hee; Hwang, Sun Hwan; Kim, Jin Soo; Lee, Bong Hoon; Yoon, Hyo Geun; Park, Hyung Soon; Baek, Seung Joo; Cho, Yun Seok; Kwak, Noh Jung; Sohn, Hyun Chul; Moon, Seung Chan; Yoo, Kyung Dong; Jeong, Jae Goan; Kim, Jin Woong; Hong, Sung Joo; Park, Sung Wook.
2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2006. p. 32-33 1705202 (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology
AU - Chung, Sung Woong
AU - Lee, Sang Don
AU - Jang, Se Aug
AU - Yoo, Min Soo
AU - Kim, Kwang Ok
AU - Chung, Chai O.
AU - Cho, Sung Yoon
AU - Cho, Heung Jae
AU - Lee, Lae Hee
AU - Hwang, Sun Hwan
AU - Kim, Jin Soo
AU - Lee, Bong Hoon
AU - Yoon, Hyo Geun
AU - Park, Hyung Soon
AU - Baek, Seung Joo
AU - Cho, Yun Seok
AU - Kwak, Noh Jung
AU - Sohn, Hyun Chul
AU - Moon, Seung Chan
AU - Yoo, Kyung Dong
AU - Jeong, Jae Goan
AU - Kim, Jin Woong
AU - Hong, Sung Joo
AU - Park, Sung Wook
PY - 2006/1/1
Y1 - 2006/1/1
N2 - Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.
AB - Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.
UR - http://www.scopus.com/inward/record.url?scp=41149147144&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=41149147144&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:41149147144
SN - 1424400058
SN - 9781424400058
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 32
EP - 33
BT - 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
ER -