@inproceedings{7cae7950801f45fab7d8eb4450ca8f39,
title = "Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology",
abstract = "Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.",
author = "Chung, {Sung Woong} and Lee, {Sang Don} and Jang, {Se Aug} and Yoo, {Min Soo} and Kim, {Kwang Ok} and Chung, {Chai O.} and Cho, {Sung Yoon} and Cho, {Heung Jae} and Lee, {Lae Hee} and Hwang, {Sun Hwan} and Kim, {Jin Soo} and Lee, {Bong Hoon} and Yoon, {Hyo Geun} and Park, {Hyung Soon} and Baek, {Seung Joo} and Cho, {Yun Seok} and Kwak, {Noh Jung} and Sohn, {Hyun Chul} and Moon, {Seung Chan} and Yoo, {Kyung Dong} and Jeong, {Jae Goan} and Kim, {Jin Woong} and Hong, {Sung Joo} and Park, {Sung Wook}",
year = "2006",
doi = "10.1109/vlsit.2006.1705202",
language = "English",
isbn = "1424400058",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "32--33",
booktitle = "2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers",
address = "United States",
note = "2006 Symposium on VLSI Technology, VLSIT ; Conference date: 13-06-2006 Through 15-06-2006",
}