Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μa/μm

Wei Yip Loh, Kanghoon Jeon, Chang Yong Kang, Jungwoo Oh, Tsu Jae King Liu, Hsing Huang Tseng, Wade Xiong, Prashant Majhi, Raj Jammy, Chenming Hu

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)


Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [Lg] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (ION)) > 100 μA/μm with ION/IOFF > 105 at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

Original languageEnglish
Pages (from-to)22-27
Number of pages6
JournalSolid-State Electronics
Issue number1
Publication statusPublished - 2011 Nov

Bibliographical note

Funding Information:
This paper is based upon work supported by the Defense Advanced Research Project Agency under a SPAWAR Systems Center, San Diego contract, #N66001-08-C-2022.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering


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