Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μa/μm

Wei Yip Loh; Kanghoon Jeon; Chang Yong Kang; Jungwoo Oh; Tsu Jae King Liu; Hsing Huang Tseng; Wade Xiong; Prashant Majhi; Raj Jammy; Chenming Hu

doi:10.1016/j.sse.2011.06.019

Highly scaled (L_g ∼ 56 nm) gate-last Si tunnel field-effect transistors with I_ON > 100 μa/μm

Wei Yip Loh, Kanghoon Jeon, Chang Yong Kang, Jungwoo Oh, Tsu Jae King Liu, Hsing Huang Tseng, Wade Xiong, Prashant Majhi, Raj Jammy, Chenming Hu

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [L_g] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (I_ON)) > 100 μA/μm with I_ON/I_OFF > 10⁵ at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

Original language	English
Pages (from-to)	22-27
Number of pages	6
Journal	Solid-State Electronics
Volume	65-66
Issue number	1
DOIs	https://doi.org/10.1016/j.sse.2011.06.019
Publication status	Published - 2011 Nov

Bibliographical note

Funding Information:
This paper is based upon work supported by the Defense Advanced Research Project Agency under a SPAWAR Systems Center, San Diego contract, #N66001-08-C-2022.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

Access to Document

10.1016/j.sse.2011.06.019

Cite this

@article{1cde566bedf14b7ca2c6f77f79488f6f,

title = "Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μa/μm",

abstract = "Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [Lg] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (ION)) > 100 μA/μm with ION/IOFF > 105 at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.",

author = "Loh, {Wei Yip} and Kanghoon Jeon and Kang, {Chang Yong} and Jungwoo Oh and {King Liu}, {Tsu Jae} and Tseng, {Hsing Huang} and Wade Xiong and Prashant Majhi and Raj Jammy and Chenming Hu",

note = "Funding Information: This paper is based upon work supported by the Defense Advanced Research Project Agency under a SPAWAR Systems Center, San Diego contract, #N66001-08-C-2022.",

year = "2011",

month = nov,

doi = "10.1016/j.sse.2011.06.019",

language = "English",

volume = "65-66",

pages = "22--27",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

number = "1",

}

TY - JOUR

T1 - Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μa/μm

AU - Loh, Wei Yip

AU - Jeon, Kanghoon

AU - Kang, Chang Yong

AU - Oh, Jungwoo

AU - King Liu, Tsu Jae

AU - Tseng, Hsing Huang

AU - Xiong, Wade

AU - Majhi, Prashant

AU - Jammy, Raj

AU - Hu, Chenming

N1 - Funding Information: This paper is based upon work supported by the Defense Advanced Research Project Agency under a SPAWAR Systems Center, San Diego contract, #N66001-08-C-2022.

PY - 2011/11

Y1 - 2011/11

N2 - Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [Lg] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (ION)) > 100 μA/μm with ION/IOFF > 105 at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

AB - Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [Lg] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (ION)) > 100 μA/μm with ION/IOFF > 105 at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

UR - http://www.scopus.com/inward/record.url?scp=80054015507&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80054015507&partnerID=8YFLogxK

U2 - 10.1016/j.sse.2011.06.019

DO - 10.1016/j.sse.2011.06.019

M3 - Article

AN - SCOPUS:80054015507

SN - 0038-1101

VL - 65-66

SP - 22

EP - 27

JO - Solid-State Electronics

JF - Solid-State Electronics

IS - 1

ER -