Abstract
We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (VT) shift of the DG TFT after 3 h of positivebias temperature stress (VGS = +20 V, V DS = +0.1 V, and Temperature = 60 °C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); VGS =.20 V, VDS = +10 V, and Temperature = 60 °C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is.9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe (.11.1 V). However, it remains as small as.0.7 V for the DG TFT.
| Original language | English |
|---|---|
| Article number | 5491056 |
| Pages (from-to) | 812-814 |
| Number of pages | 3 |
| Journal | IEEE Electron Device Letters |
| Volume | 31 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 2010 Aug 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Highly stable double-gate Ga-In-Zn-O thin-film transistor. / Son, Kyoung Seok; Jung, Ji Sim; Lee, Kwang Hee; Kim, Tae Sang; Park, Joon Seok; Park, Keechan; Kwon, Jang Yeon; Koo, Bonwon; Lee, Sang Yoon.
In: IEEE Electron Device Letters, Vol. 31, No. 8, 5491056, 01.08.2010, p. 812-814.Research output: Contribution to journal › Article
TY - JOUR
T1 - Highly stable double-gate Ga-In-Zn-O thin-film transistor
AU - Son, Kyoung Seok
AU - Jung, Ji Sim
AU - Lee, Kwang Hee
AU - Kim, Tae Sang
AU - Park, Joon Seok
AU - Park, Keechan
AU - Kwon, Jang Yeon
AU - Koo, Bonwon
AU - Lee, Sang Yoon
PY - 2010/8/1
Y1 - 2010/8/1
N2 - We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (VT) shift of the DG TFT after 3 h of positivebias temperature stress (VGS = +20 V, V DS = +0.1 V, and Temperature = 60 °C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); VGS =.20 V, VDS = +10 V, and Temperature = 60 °C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is.9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe (.11.1 V). However, it remains as small as.0.7 V for the DG TFT.
AB - We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (VT) shift of the DG TFT after 3 h of positivebias temperature stress (VGS = +20 V, V DS = +0.1 V, and Temperature = 60 °C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); VGS =.20 V, VDS = +10 V, and Temperature = 60 °C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is.9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe (.11.1 V). However, it remains as small as.0.7 V for the DG TFT.
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U2 - 10.1109/LED.2010.2050294
DO - 10.1109/LED.2010.2050294
M3 - Article
AN - SCOPUS:77955172950
VL - 31
SP - 812
EP - 814
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
SN - 0741-3106
IS - 8
M1 - 5491056
ER -