Highly stable double-gate Ga-In-Zn-O thin-film transistor

Kyoung Seok Son; Ji Sim Jung; Kwang Hee Lee; Tae Sang Kim; Joon Seok Park; Keechan Park; Jang Yeon Kwon; Bonwon Koo; Sang Yoon Lee

doi:10.1109/LED.2010.2050294

Highly stable double-gate Ga-In-Zn-O thin-film transistor

Kyoung Seok Son, Ji Sim Jung, Kwang Hee Lee, Tae Sang Kim, Joon Seok Park, Keechan Park, Jang Yeon Kwon, Bonwon Koo, Sang Yoon Lee

School of Integrated Technology

Research output: Contribution to journal › Article

39 Citations (Scopus)

Abstract

We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (V_T) shift of the DG TFT after 3 h of positivebias temperature stress (V_GS = +20 V, V _DS = +0.1 V, and Temperature = 60 °C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); V_GS =.20 V, V_DS = +10 V, and Temperature = 60 °C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is.9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe (.11.1 V). However, it remains as small as.0.7 V for the DG TFT.

Original language	English
Article number	5491056
Pages (from-to)	812-814
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	31
Issue number	8
DOIs	https://doi.org/10.1109/LED.2010.2050294
Publication status	Published - 2010 Aug 1

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All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Son, K. S., Jung, J. S., Lee, K. H., Kim, T. S., Park, J. S., Park, K., Kwon, J. Y., Koo, B., & Lee, S. Y. (2010). Highly stable double-gate Ga-In-Zn-O thin-film transistor. IEEE Electron Device Letters, 31(8), 812-814. [5491056]. https://doi.org/10.1109/LED.2010.2050294

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abstract = "We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (VT) shift of the DG TFT after 3 h of positivebias temperature stress (VGS = +20 V, V DS = +0.1 V, and Temperature = 60 °C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); VGS =.20 V, VDS = +10 V, and Temperature = 60 °C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is.9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe (.11.1 V). However, it remains as small as.0.7 V for the DG TFT.",

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AU - Park, Keechan

AU - Kwon, Jang Yeon

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Access to Document

10.1109/LED.2010.2050294