TY - GEN
T1 - HIOS
T2 - 2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014
AU - Jung, Myoungsoo
AU - Choi, Wonil
AU - Srikantaiah, Shekhar
AU - Yoo, Joonhyuk
AU - Kandemir, Mahmut T.
PY - 2014
Y1 - 2014
N2 - Garbage collection (GC) and resource contention on I/O buses (channels) are among the critical bottlenecks in Solid State Disks (SSDs) that cannot be easily hidden. Most existing I/O scheduling algorithms in the host interface logic (HIL) of state-of-the-art SSDs are oblivious to such low-level performance bottlenecks in SSDs. As a result, SSDs may violate quality of service (QoS) requirements by not being able to meet the deadlines of I/O requests. In this paper, we propose a novel host interface I/O scheduler that is both GC-aware and QoS-aware. The proposed scheduler redistributes the GC overheads across non-critical I/O requests and reduces channel resource contention. Our experiments with workloads from various application domains reveal that the proposed scheduler reduces the standard deviation for latency over state-of-the-art I/O schedulers used in the HIL by 52.5%, and the worst-case latency by 86.6%. In addition, for I/O requests with sizes smaller than a superpage, our proposed scheduler avoids channel resource conflicts and reduces latency by 29.2% compared to the state-of-the-art.
AB - Garbage collection (GC) and resource contention on I/O buses (channels) are among the critical bottlenecks in Solid State Disks (SSDs) that cannot be easily hidden. Most existing I/O scheduling algorithms in the host interface logic (HIL) of state-of-the-art SSDs are oblivious to such low-level performance bottlenecks in SSDs. As a result, SSDs may violate quality of service (QoS) requirements by not being able to meet the deadlines of I/O requests. In this paper, we propose a novel host interface I/O scheduler that is both GC-aware and QoS-aware. The proposed scheduler redistributes the GC overheads across non-critical I/O requests and reduces channel resource contention. Our experiments with workloads from various application domains reveal that the proposed scheduler reduces the standard deviation for latency over state-of-the-art I/O schedulers used in the HIL by 52.5%, and the worst-case latency by 86.6%. In addition, for I/O requests with sizes smaller than a superpage, our proposed scheduler avoids channel resource conflicts and reduces latency by 29.2% compared to the state-of-the-art.
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U2 - 10.1109/ISCA.2014.6853216
DO - 10.1109/ISCA.2014.6853216
M3 - Conference contribution
AN - SCOPUS:84905507456
SN - 9781479943968
T3 - Proceedings - International Symposium on Computer Architecture
SP - 289
EP - 300
BT - 41st Annual International Symposium on Computer Architecture, ISCA 2014 - Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 14 June 2014 through 18 June 2014
ER -