Recently, the demand for artificial intelligence such as IoT, autonomous vehicles and cloud is rapidly increased, and intelligent processors are expected to be used in all objects such as home appliances and automobiles. Intelligent processors are composed of multiple identical cores for parallel computation and acceleration of neural networks to implement artificial intelligence services. Due to the high degree of integration and the increase of test complexity in intelligent processors, efficient parallel testing is required. In this paper, a new test access mechanism is proposed to test the multiple identical cores. The proposed method solves the problem of the previous parallel test access mechanism in low-yield system without additional hardware and can test multiple identical cores at the cost of testing one core.
|Title of host publication||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2021|
|Event||18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of|
Duration: 2021 Oct 6 → 2021 Oct 9
|Name||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Conference||18th International System-on-Chip Design Conference, ISOCC 2021|
|Country/Territory||Korea, Republic of|
|Period||21/10/6 → 21/10/9|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by the MOTIE and KEIT [20012010, Design for Test of Intelligent Processors].
© 2021 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Information Systems
- Hardware and Architecture
- Electrical and Electronic Engineering