Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions

Kwan Yong Lim, Se Aug Jang, Yong Soo Kim, Heung Jae Cho, Jae Geun Oh, Su Ock Chung, Sung Joon Lee, Woo Kyung Sun, Jai Bum Suh, Hong Seon Yang, Hyun Chul Sohn

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurement, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO2/nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.

Original languageEnglish
Article number1315376
Pages (from-to)485-488
Number of pages4
JournalIEEE International Reliability Physics Symposium Proceedings
Volume2004-January
Issue numberJanuary
DOIs
Publication statusPublished - 2004 Jan 1
Event42nd Annual IEEE International Reliability Physics Symposium, IRPS 2004 - Phoenix, United States
Duration: 2004 Apr 252004 Apr 29

Fingerprint

Dynamic random access storage
Transistors
Nitrides
Leakage currents
Drain current
Degradation
Defects
Oxides
Electric potential

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Lim, Kwan Yong ; Jang, Se Aug ; Kim, Yong Soo ; Cho, Heung Jae ; Oh, Jae Geun ; Chung, Su Ock ; Lee, Sung Joon ; Sun, Woo Kyung ; Suh, Jai Bum ; Yang, Hong Seon ; Sohn, Hyun Chul. / Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions. In: IEEE International Reliability Physics Symposium Proceedings. 2004 ; Vol. 2004-January, No. January. pp. 485-488.
@article{cd0fb158a5ae41e0b8ff05e963e1ba55,
title = "Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions",
abstract = "We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurement, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO2/nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.",
author = "Lim, {Kwan Yong} and Jang, {Se Aug} and Kim, {Yong Soo} and Cho, {Heung Jae} and Oh, {Jae Geun} and Chung, {Su Ock} and Lee, {Sung Joon} and Sun, {Woo Kyung} and Suh, {Jai Bum} and Yang, {Hong Seon} and Sohn, {Hyun Chul}",
year = "2004",
month = "1",
day = "1",
doi = "10.1109/RELPHY.2004.1315376",
language = "English",
volume = "2004-January",
pages = "485--488",
journal = "IEEE International Reliability Physics Symposium Proceedings",
issn = "1541-7026",
number = "January",

}

Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions. / Lim, Kwan Yong; Jang, Se Aug; Kim, Yong Soo; Cho, Heung Jae; Oh, Jae Geun; Chung, Su Ock; Lee, Sung Joon; Sun, Woo Kyung; Suh, Jai Bum; Yang, Hong Seon; Sohn, Hyun Chul.

In: IEEE International Reliability Physics Symposium Proceedings, Vol. 2004-January, No. January, 1315376, 01.01.2004, p. 485-488.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions

AU - Lim, Kwan Yong

AU - Jang, Se Aug

AU - Kim, Yong Soo

AU - Cho, Heung Jae

AU - Oh, Jae Geun

AU - Chung, Su Ock

AU - Lee, Sung Joon

AU - Sun, Woo Kyung

AU - Suh, Jai Bum

AU - Yang, Hong Seon

AU - Sohn, Hyun Chul

PY - 2004/1/1

Y1 - 2004/1/1

N2 - We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurement, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO2/nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.

AB - We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurement, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO2/nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.

UR - http://www.scopus.com/inward/record.url?scp=84932093159&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84932093159&partnerID=8YFLogxK

U2 - 10.1109/RELPHY.2004.1315376

DO - 10.1109/RELPHY.2004.1315376

M3 - Conference article

AN - SCOPUS:84932093159

VL - 2004-January

SP - 485

EP - 488

JO - IEEE International Reliability Physics Symposium Proceedings

JF - IEEE International Reliability Physics Symposium Proceedings

SN - 1541-7026

IS - January

M1 - 1315376

ER -