Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions

Kwan Yong Lim, Se Aug Jang, Yong Soo Kim, Heung Jae Cho, Jae Geun Oh, Su Ock Chung, Sung Joon Lee, Woo Kyung Sun, Jai Bum Suh, Hong Seon Yang, Hyun Chul Sohn

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurements, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO2/nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.

Original languageEnglish
Pages (from-to)485-488
Number of pages4
JournalAnnual Proceedings - Reliability Physics (Symposium)
Publication statusPublished - 2004
Event2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual - Phoenix, AZ., United States
Duration: 2004 Apr 252004 Apr 29

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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