Impact of millisecond flash-assisted rapid thermal annealing on SiGe heterostructure channel pMOSFETs with a high-k/metal gate

Se Hoon Lee, Prashant Majhi, Domingo A. Ferrer, Pui Yee Hung, Jeff Huang, Jungwoo Oh, Wei Yip Loh, Barry Sassman, Byoung Gi Min, Hsing Huang Tseng, Rusty Harris, Gennadi Bersuker, Paul D. Kirsch, Raj Jammy, Sanjay K. Banerjee

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high-k/metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted p+ junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high-k/metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation.

Original languageEnglish
Article number5966326
Pages (from-to)2917-2923
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume58
Issue number9
DOIs
Publication statusPublished - 2011 Sep

Bibliographical note

Funding Information:
Manuscript received October 21, 2010; accepted June 7, 2011. Date of publication July 29, 2011; date of current version August 24, 2011. This work was supported in part by the Defense Advanced Research Projects Agency under Grant HR0011-08-1-0050. The review of this paper was arranged by Editor M. Ieong. S.-H. Lee was with the Microelectronic Research Center, The University of Texas at Austin, Austin, TX 78758 USA. He is now with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: sehoon2@utexas.edu). P. Majhi was with SEMATECH, Austin, TX 78741 USA. He is now with Intel Corporation, Santa Clara, CA 95054 USA. D. A. Ferrer and S. K. Banerjee are with the Microelectronic Research Center, The University of Texas at Austin, Austin, TX 78758 USA. P.-Y. Hung, J. Huang, J. Oh, W.-Y. Loh, B. Sassman, B.-G. Min, G. Bersuker, P. D. Kirsch, and R. Jammy are with SEMATECH, Austin, TX 78741 USA (e-mail: gennadi.bersuker@sematech.org) H.-H. Tseng was with SEMATECH, Austin, TX 78741 USA. He is now with Texas State University, San Marcos, TX 78666 USA. R. Harris was with SEMATECH, Austin, TX 78741 USA. He is now with Texas A&M University, College Station, TX 77843 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2159862

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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